1; RUN: llc -mtriple=aarch64-none-linux-gnu < %s | FileCheck %s
2
3@var = global i1 0
4
5define i32 @test_sextloadi32() {
6; CHECK: test_sextloadi32
7
8  %val = load i1* @var
9  %ret = sext i1 %val to i32
10; CHECK: ldrb {{w[0-9]+}}, [{{x[0-9]+}}, #:lo12:var]
11; CHECK: sbfx {{x[0-9]+}}, {{x[0-9]+}}, #0, #1
12
13  ret i32 %ret
14; CHECK: ret
15}
16
17define i64 @test_sextloadi64() {
18; CHECK: test_sextloadi64
19
20  %val = load i1* @var
21  %ret = sext i1 %val to i64
22; CHECK: ldrb {{w[0-9]+}}, [{{x[0-9]+}}, #:lo12:var]
23; CHECK: sbfx {{x[0-9]+}}, {{x[0-9]+}}, #0, #1
24
25  ret i64 %ret
26; CHECK: ret
27}
28
29define i32 @test_zextloadi32() {
30; CHECK: test_zextloadi32
31
32; It's not actually necessary that "ret" is next, but as far as LLVM
33; is concerned only 0 or 1 should be loadable so no extension is
34; necessary.
35  %val = load i1* @var
36  %ret = zext i1 %val to i32
37; CHECK: ldrb {{w[0-9]+}}, [{{x[0-9]+}}, #:lo12:var]
38
39  ret i32 %ret
40; CHECK-NEXT: ret
41}
42
43define i64 @test_zextloadi64() {
44; CHECK: test_zextloadi64
45
46; It's not actually necessary that "ret" is next, but as far as LLVM
47; is concerned only 0 or 1 should be loadable so no extension is
48; necessary.
49  %val = load i1* @var
50  %ret = zext i1 %val to i64
51; CHECK: ldrb {{w[0-9]+}}, [{{x[0-9]+}}, #:lo12:var]
52
53  ret i64 %ret
54; CHECK-NEXT: ret
55}
56