1; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s
2; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu -mattr=-fp-armv8 | FileCheck --check-prefix=CHECK-NOFP %s
3
4define i32 @test_select_i32(i1 %bit, i32 %a, i32 %b) {
5; CHECK-LABEL: test_select_i32:
6  %val = select i1 %bit, i32 %a, i32 %b
7; CHECK: movz [[ONE:w[0-9]+]], #1
8; CHECK: tst w0, [[ONE]]
9; CHECK-NEXT: csel w0, w1, w2, ne
10
11  ret i32 %val
12}
13
14define i64 @test_select_i64(i1 %bit, i64 %a, i64 %b) {
15; CHECK-LABEL: test_select_i64:
16  %val = select i1 %bit, i64 %a, i64 %b
17; CHECK: movz [[ONE:w[0-9]+]], #1
18; CHECK: tst w0, [[ONE]]
19; CHECK-NEXT: csel x0, x1, x2, ne
20
21  ret i64 %val
22}
23
24define float @test_select_float(i1 %bit, float %a, float %b) {
25; CHECK-LABEL: test_select_float:
26  %val = select i1 %bit, float %a, float %b
27; CHECK: movz [[ONE:w[0-9]+]], #1
28; CHECK: tst w0, [[ONE]]
29; CHECK-NEXT: fcsel s0, s0, s1, ne
30; CHECK-NOFP-NOT: fcsel
31  ret float %val
32}
33
34define double @test_select_double(i1 %bit, double %a, double %b) {
35; CHECK-LABEL: test_select_double:
36  %val = select i1 %bit, double %a, double %b
37; CHECK: movz [[ONE:w[0-9]+]], #1
38; CHECK: tst w0, [[ONE]]
39; CHECK-NEXT: fcsel d0, d0, d1, ne
40; CHECK-NOFP-NOT: fcsel
41
42  ret double %val
43}
44
45define i32 @test_brcond(i1 %bit) {
46; CHECK-LABEL: test_brcond:
47  br i1 %bit, label %true, label %false
48; CHECK: tbz {{w[0-9]+}}, #0, .LBB
49
50true:
51  ret i32 0
52false:
53  ret i32 42
54}
55
56define i1 @test_setcc_float(float %lhs, float %rhs) {
57; CHECK: test_setcc_float
58  %val = fcmp oeq float %lhs, %rhs
59; CHECK: fcmp s0, s1
60; CHECK: csinc w0, wzr, wzr, ne
61; CHECK-NOFP-NOT: fcmp
62  ret i1 %val
63}
64
65define i1 @test_setcc_double(double %lhs, double %rhs) {
66; CHECK: test_setcc_double
67  %val = fcmp oeq double %lhs, %rhs
68; CHECK: fcmp d0, d1
69; CHECK: csinc w0, wzr, wzr, ne
70; CHECK-NOFP-NOT: fcmp
71  ret i1 %val
72}
73
74define i1 @test_setcc_i32(i32 %lhs, i32 %rhs) {
75; CHECK: test_setcc_i32
76  %val = icmp ugt i32 %lhs, %rhs
77; CHECK: cmp w0, w1
78; CHECK: csinc w0, wzr, wzr, ls
79  ret i1 %val
80}
81
82define i1 @test_setcc_i64(i64 %lhs, i64 %rhs) {
83; CHECK: test_setcc_i64
84  %val = icmp ne i64 %lhs, %rhs
85; CHECK: cmp x0, x1
86; CHECK: csinc w0, wzr, wzr, eq
87  ret i1 %val
88}
89