1; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s 2; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu -mattr=-fp-armv8 | FileCheck --check-prefix=CHECK-NOFP %s 3 4%myStruct = type { i64 , i8, i32 } 5 6@var8 = global i8 0 7@var32 = global i32 0 8@var64 = global i64 0 9@var128 = global i128 0 10@varfloat = global float 0.0 11@vardouble = global double 0.0 12@varstruct = global %myStruct zeroinitializer 13 14define void @take_i8s(i8 %val1, i8 %val2) { 15; CHECK-LABEL: take_i8s: 16 store i8 %val2, i8* @var8 17 ; Not using w1 may be technically allowed, but it would indicate a 18 ; problem in itself. 19; CHECK: strb w1, [{{x[0-9]+}}, #:lo12:var8] 20 ret void 21} 22 23define void @add_floats(float %val1, float %val2) { 24; CHECK-LABEL: add_floats: 25 %newval = fadd float %val1, %val2 26; CHECK: fadd [[ADDRES:s[0-9]+]], s0, s1 27; CHECK-NOFP-NOT: fadd 28 store float %newval, float* @varfloat 29; CHECK: str [[ADDRES]], [{{x[0-9]+}}, #:lo12:varfloat] 30 ret void 31} 32 33; byval pointers should be allocated to the stack and copied as if 34; with memcpy. 35define void @take_struct(%myStruct* byval %structval) { 36; CHECK-LABEL: take_struct: 37 %addr0 = getelementptr %myStruct* %structval, i64 0, i32 2 38 %addr1 = getelementptr %myStruct* %structval, i64 0, i32 0 39 40 %val0 = load volatile i32* %addr0 41 ; Some weird move means x0 is used for one access 42; CHECK: ldr [[REG32:w[0-9]+]], [{{x[0-9]+|sp}}, #12] 43 store volatile i32 %val0, i32* @var32 44; CHECK: str [[REG32]], [{{x[0-9]+}}, #:lo12:var32] 45 46 %val1 = load volatile i64* %addr1 47; CHECK: ldr [[REG64:x[0-9]+]], [{{x[0-9]+|sp}}] 48 store volatile i64 %val1, i64* @var64 49; CHECK: str [[REG64]], [{{x[0-9]+}}, #:lo12:var64] 50 51 ret void 52} 53 54; %structval should be at sp + 16 55define void @check_byval_align(i32* byval %ignore, %myStruct* byval align 16 %structval) { 56; CHECK-LABEL: check_byval_align: 57 58 %addr0 = getelementptr %myStruct* %structval, i64 0, i32 2 59 %addr1 = getelementptr %myStruct* %structval, i64 0, i32 0 60 61 %val0 = load volatile i32* %addr0 62 ; Some weird move means x0 is used for one access 63; CHECK: add x[[STRUCTVAL_ADDR:[0-9]+]], sp, #16 64; CHECK: ldr [[REG32:w[0-9]+]], [x[[STRUCTVAL_ADDR]], #12] 65 store i32 %val0, i32* @var32 66; CHECK: str [[REG32]], [{{x[0-9]+}}, #:lo12:var32] 67 68 %val1 = load volatile i64* %addr1 69; CHECK: ldr [[REG64:x[0-9]+]], [sp, #16] 70 store i64 %val1, i64* @var64 71; CHECK: str [[REG64]], [{{x[0-9]+}}, #:lo12:var64] 72 73 ret void 74} 75 76define i32 @return_int() { 77; CHECK-LABEL: return_int: 78 %val = load i32* @var32 79 ret i32 %val 80; CHECK: ldr w0, [{{x[0-9]+}}, #:lo12:var32] 81 ; Make sure epilogue follows 82; CHECK-NEXT: ret 83} 84 85define double @return_double() { 86; CHECK-LABEL: return_double: 87 ret double 3.14 88; CHECK: ldr d0, [{{x[0-9]+}}, #:lo12:.LCPI 89; CHECK-NOFP-NOT: ldr d0, 90} 91 92; This is the kind of IR clang will produce for returning a struct 93; small enough to go into registers. Not all that pretty, but it 94; works. 95define [2 x i64] @return_struct() { 96; CHECK-LABEL: return_struct: 97 %addr = bitcast %myStruct* @varstruct to [2 x i64]* 98 %val = load [2 x i64]* %addr 99 ret [2 x i64] %val 100; CHECK: ldr x0, [{{x[0-9]+}}, #:lo12:varstruct] 101 ; Odd register regex below disallows x0 which we want to be live now. 102; CHECK: add {{x[1-9][0-9]*}}, {{x[1-9][0-9]*}}, #:lo12:varstruct 103; CHECK-NEXT: ldr x1, [{{x[1-9][0-9]*}}, #8] 104 ; Make sure epilogue immediately follows 105; CHECK-NEXT: ret 106} 107 108; Large structs are passed by reference (storage allocated by caller 109; to preserve value semantics) in x8. Strictly this only applies to 110; structs larger than 16 bytes, but C semantics can still be provided 111; if LLVM does it to %myStruct too. So this is the simplest check 112define void @return_large_struct(%myStruct* sret %retval) { 113; CHECK-LABEL: return_large_struct: 114 %addr0 = getelementptr %myStruct* %retval, i64 0, i32 0 115 %addr1 = getelementptr %myStruct* %retval, i64 0, i32 1 116 %addr2 = getelementptr %myStruct* %retval, i64 0, i32 2 117 118 store i64 42, i64* %addr0 119 store i8 2, i8* %addr1 120 store i32 9, i32* %addr2 121; CHECK: str {{x[0-9]+}}, [x8] 122; CHECK: strb {{w[0-9]+}}, [x8, #8] 123; CHECK: str {{w[0-9]+}}, [x8, #12] 124 125 ret void 126} 127 128; This struct is just too far along to go into registers: (only x7 is 129; available, but it needs two). Also make sure that %stacked doesn't 130; sneak into x7 behind. 131define i32 @struct_on_stack(i8 %var0, i16 %var1, i32 %var2, i64 %var3, i128 %var45, 132 i32* %var6, %myStruct* byval %struct, i32* byval %stacked, 133 double %notstacked) { 134; CHECK-LABEL: struct_on_stack: 135 %addr = getelementptr %myStruct* %struct, i64 0, i32 0 136 %val64 = load volatile i64* %addr 137 store volatile i64 %val64, i64* @var64 138 ; Currently nothing on local stack, so struct should be at sp 139; CHECK: ldr [[VAL64:x[0-9]+]], [sp] 140; CHECK: str [[VAL64]], [{{x[0-9]+}}, #:lo12:var64] 141 142 store volatile double %notstacked, double* @vardouble 143; CHECK-NOT: ldr d0 144; CHECK: str d0, [{{x[0-9]+}}, #:lo12:vardouble 145; CHECK-NOFP-NOT: str d0, 146 147 %retval = load volatile i32* %stacked 148 ret i32 %retval 149; CHECK: ldr w0, [sp, #16] 150} 151 152define void @stacked_fpu(float %var0, double %var1, float %var2, float %var3, 153 float %var4, float %var5, float %var6, float %var7, 154 float %var8) { 155; CHECK-LABEL: stacked_fpu: 156 store float %var8, float* @varfloat 157 ; Beware as above: the offset would be different on big-endian 158 ; machines if the first ldr were changed to use s-registers. 159; CHECK: ldr d[[VALFLOAT:[0-9]+]], [sp] 160; CHECK: str s[[VALFLOAT]], [{{x[0-9]+}}, #:lo12:varfloat] 161 162 ret void 163} 164 165; 128-bit integer types should be passed in xEVEN, xODD rather than 166; the reverse. In this case x2 and x3. Nothing should use x1. 167define i32 @check_i128_regalign(i32 %val0, i128 %val1, i32 %val2) { 168; CHECK: check_i128_regalign 169 store i128 %val1, i128* @var128 170; CHECK: str x2, [{{x[0-9]+}}, #:lo12:var128] 171; CHECK: str x3, [{{x[0-9]+}}, #8] 172 173 ret i32 %val2 174; CHECK: mov x0, x4 175} 176 177define void @check_i128_stackalign(i32 %val0, i32 %val1, i32 %val2, i32 %val3, 178 i32 %val4, i32 %val5, i32 %val6, i32 %val7, 179 i32 %stack1, i128 %stack2) { 180; CHECK: check_i128_stackalign 181 store i128 %stack2, i128* @var128 182 ; Nothing local on stack in current codegen, so first stack is 16 away 183; CHECK: add x[[REG:[0-9]+]], sp, #16 184; CHECK: ldr {{x[0-9]+}}, [x[[REG]], #8] 185 ; Important point is that we address sp+24 for second dword 186; CHECK: ldr {{x[0-9]+}}, [sp, #16] 187 ret void 188} 189 190declare void @llvm.memcpy.p0i8.p0i8.i32(i8*, i8*, i32, i32, i1) 191 192define i32 @test_extern() { 193; CHECK-LABEL: test_extern: 194 call void @llvm.memcpy.p0i8.p0i8.i32(i8* undef, i8* undef, i32 undef, i32 4, i1 0) 195; CHECK: bl memcpy 196 ret i32 0 197} 198