1; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s --check-prefix=CHECK
2
3define <8 x i8> @movi8b() {
4; CHECK-LABEL: movi8b:
5; CHECK:  movi {{v[0-9]+}}.8b, #{{0x8|8}}
6   ret <8 x i8> < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 >
7}
8
9define <16 x i8> @movi16b() {
10; CHECK-LABEL: movi16b:
11; CHECK:  movi {{v[0-9]+}}.16b, #{{0x8|8}}
12   ret <16 x i8> < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 >
13}
14
15define <2 x i32> @movi2s_lsl0() {
16; CHECK-LABEL: movi2s_lsl0:
17; CHECK: movi {{d[0-9]+}}, #0x0000ff000000ff
18   ret <2 x i32> < i32 255, i32 255 >
19}
20
21define <2 x i32> @movi2s_lsl8() {
22; CHECK-LABEL: movi2s_lsl8:
23; CHECK: movi {{d[0-9]+}}, #0x00ff000000ff00
24   ret <2 x i32> < i32 65280, i32 65280 >
25}
26
27define <2 x i32> @movi2s_lsl16() {
28; CHECK-LABEL: movi2s_lsl16:
29; CHECK: movi {{d[0-9]+}}, #0xff000000ff0000
30   ret <2 x i32> < i32 16711680, i32 16711680 >
31
32}
33
34define <2 x i32> @movi2s_lsl24() {
35; CHECK-LABEL: movi2s_lsl24:
36; CHECK: movi {{d[0-9]+}}, #0xff000000ff000000
37   ret <2 x i32> < i32 4278190080, i32 4278190080 >
38}
39
40define <4 x i32> @movi4s_lsl0() {
41; CHECK-LABEL: movi4s_lsl0:
42; CHECK: movi {{v[0-9]+}}.2d, #0x0000ff000000ff
43   ret <4 x i32> < i32 255, i32 255, i32 255, i32 255 >
44}
45
46define <4 x i32> @movi4s_lsl8() {
47; CHECK-LABEL: movi4s_lsl8:
48; CHECK: movi {{v[0-9]+}}.2d, #0x00ff000000ff00
49   ret <4 x i32> < i32 65280, i32 65280, i32 65280, i32 65280 >
50}
51
52define <4 x i32> @movi4s_lsl16() {
53; CHECK-LABEL: movi4s_lsl16:
54; CHECK:  movi {{v[0-9]+}}.2d, #0xff000000ff0000
55   ret <4 x i32> < i32 16711680, i32 16711680, i32 16711680, i32 16711680 >
56
57}
58
59define <4 x i32> @movi4s_lsl24() {
60; CHECK-LABEL: movi4s_lsl24:
61; CHECK:  movi {{v[0-9]+}}.2d, #0xff000000ff000000
62   ret <4 x i32> < i32 4278190080, i32 4278190080, i32 4278190080, i32 4278190080 >
63}
64
65define <4 x i16> @movi4h_lsl0() {
66; CHECK-LABEL: movi4h_lsl0:
67; CHECK:  movi {{d[0-9]+}}, #0xff00ff00ff00ff
68   ret <4 x i16> < i16 255, i16 255, i16 255, i16 255 >
69}
70
71define <4 x i16> @movi4h_lsl8() {
72; CHECK-LABEL: movi4h_lsl8:
73; CHECK: movi d0, #0xff00ff00ff00ff00
74   ret <4 x i16> < i16 65280, i16 65280, i16 65280, i16 65280 >
75}
76
77define <8 x i16> @movi8h_lsl0() {
78; CHECK-LABEL: movi8h_lsl0:
79; CHECK: movi v0.2d, #0xff00ff00ff00ff
80   ret <8 x i16> < i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255 >
81}
82
83define <8 x i16> @movi8h_lsl8() {
84; CHECK-LABEL: movi8h_lsl8:
85; CHECK: movi v0.2d, #0xff00ff00ff00ff00
86   ret <8 x i16> < i16 65280, i16 65280, i16 65280, i16 65280, i16 65280, i16 65280, i16 65280, i16 65280 >
87}
88
89
90define <2 x i32> @mvni2s_lsl0() {
91; CHECK-LABEL: mvni2s_lsl0:
92; CHECK:  mvni {{v[0-9]+}}.2s, #{{0x10|16}}
93   ret <2 x i32> < i32 4294967279, i32 4294967279 >
94}
95
96define <2 x i32> @mvni2s_lsl8() {
97; CHECK-LABEL: mvni2s_lsl8:
98; CHECK:  mvni {{v[0-9]+}}.2s, #{{0x10|16}}, lsl #8
99   ret <2 x i32> < i32 4294963199, i32 4294963199 >
100}
101
102define <2 x i32> @mvni2s_lsl16() {
103; CHECK-LABEL: mvni2s_lsl16:
104; CHECK:  mvni {{v[0-9]+}}.2s, #{{0x10|16}}, lsl #16
105   ret <2 x i32> < i32 4293918719, i32 4293918719 >
106}
107
108define <2 x i32> @mvni2s_lsl24() {
109; CHECK-LABEL: mvni2s_lsl24:
110; CHECK:  mvni {{v[0-9]+}}.2s, #{{0x10|16}}, lsl #24
111   ret <2 x i32> < i32 4026531839, i32 4026531839 >
112}
113
114define <4 x i32> @mvni4s_lsl0() {
115; CHECK-LABEL: mvni4s_lsl0:
116; CHECK:  mvni {{v[0-9]+}}.4s, #{{0x10|16}}
117   ret <4 x i32> < i32 4294967279, i32 4294967279, i32 4294967279, i32 4294967279 >
118}
119
120define <4 x i32> @mvni4s_lsl8() {
121; CHECK-LABEL: mvni4s_lsl8:
122; CHECK:  mvni {{v[0-9]+}}.4s, #{{0x10|16}}, lsl #8
123   ret <4 x i32> < i32 4294963199, i32 4294963199, i32 4294963199, i32 4294963199 >
124}
125
126define <4 x i32> @mvni4s_lsl16() {
127; CHECK-LABEL: mvni4s_lsl16:
128; CHECK:  mvni {{v[0-9]+}}.4s, #{{0x10|16}}, lsl #16
129   ret <4 x i32> < i32 4293918719, i32 4293918719, i32 4293918719, i32 4293918719 >
130
131}
132
133define <4 x i32> @mvni4s_lsl24() {
134; CHECK-LABEL: mvni4s_lsl24:
135; CHECK:  mvni {{v[0-9]+}}.4s, #{{0x10|16}}, lsl #24
136   ret <4 x i32> < i32 4026531839, i32 4026531839, i32 4026531839, i32 4026531839 >
137}
138
139
140define <4 x i16> @mvni4h_lsl0() {
141; CHECK-LABEL: mvni4h_lsl0:
142; CHECK:  mvni {{v[0-9]+}}.4h, #{{0x10|16}}
143   ret <4 x i16> < i16 65519, i16 65519, i16 65519, i16 65519 >
144}
145
146define <4 x i16> @mvni4h_lsl8() {
147; CHECK-LABEL: mvni4h_lsl8:
148; CHECK:  mvni {{v[0-9]+}}.4h, #{{0x10|16}}, lsl #8
149   ret <4 x i16> < i16 61439, i16 61439, i16 61439, i16 61439 >
150}
151
152define <8 x i16> @mvni8h_lsl0() {
153; CHECK-LABEL: mvni8h_lsl0:
154; CHECK:  mvni {{v[0-9]+}}.8h, #{{0x10|16}}
155   ret <8 x i16> < i16 65519, i16 65519, i16 65519, i16 65519, i16 65519, i16 65519, i16 65519, i16 65519 >
156}
157
158define <8 x i16> @mvni8h_lsl8() {
159; CHECK-LABEL: mvni8h_lsl8:
160; CHECK:  mvni {{v[0-9]+}}.8h, #{{0x10|16}}, lsl #8
161   ret <8 x i16> < i16 61439, i16 61439, i16 61439, i16 61439, i16 61439, i16 61439, i16 61439, i16 61439 >
162}
163
164
165define <2 x i32> @movi2s_msl8(<2 x i32> %a) {
166; CHECK-LABEL: movi2s_msl8:
167; CHECK: movi {{d[0-9]+}}, #0x00ffff0000ffff
168	ret <2 x i32> < i32 65535, i32 65535 >
169}
170
171define <2 x i32> @movi2s_msl16() {
172; CHECK-LABEL: movi2s_msl16:
173; CHECK:  movi d0, #0xffffff00ffffff
174   ret <2 x i32> < i32 16777215, i32 16777215 >
175}
176
177
178define <4 x i32> @movi4s_msl8() {
179; CHECK-LABEL: movi4s_msl8:
180; CHECK:  movi v0.2d, #0x00ffff0000ffff
181   ret <4 x i32> < i32 65535, i32 65535, i32 65535, i32 65535 >
182}
183
184define <4 x i32> @movi4s_msl16() {
185; CHECK-LABEL: movi4s_msl16:
186; CHECK:  movi v0.2d, #0xffffff00ffffff
187   ret <4 x i32> < i32 16777215, i32 16777215, i32 16777215, i32 16777215 >
188}
189
190define <2 x i32> @mvni2s_msl8() {
191; CHECK-LABEL: mvni2s_msl8:
192; CHECK:  mvni {{v[0-9]+}}.2s, #{{0x10|16}}, msl #8
193   ret <2 x i32> < i32 18446744073709547264, i32 18446744073709547264>
194}
195
196define <2 x i32> @mvni2s_msl16() {
197; CHECK-LABEL: mvni2s_msl16:
198; CHECK:  mvni {{v[0-9]+}}.2s, #{{0x10|16}}, msl #16
199   ret <2 x i32> < i32 18446744073708437504, i32 18446744073708437504>
200}
201
202define <4 x i32> @mvni4s_msl8() {
203; CHECK-LABEL: mvni4s_msl8:
204; CHECK:  mvni {{v[0-9]+}}.4s, #{{0x10|16}}, msl #8
205   ret <4 x i32> < i32 18446744073709547264, i32 18446744073709547264, i32 18446744073709547264, i32 18446744073709547264>
206}
207
208define <4 x i32> @mvni4s_msl16() {
209; CHECK-LABEL: mvni4s_msl16:
210; CHECK:  mvni {{v[0-9]+}}.4s, #{{0x10|16}}, msl #16
211   ret <4 x i32> < i32 18446744073708437504, i32 18446744073708437504, i32 18446744073708437504, i32 18446744073708437504>
212}
213
214define <2 x i64> @movi2d() {
215; CHECK-LABEL: movi2d:
216; CHECK: movi {{v[0-9]+}}.2d, #0xff0000ff0000ffff
217	ret <2 x i64> < i64 18374687574888349695, i64 18374687574888349695 >
218}
219
220define <1 x i64> @movid() {
221; CHECK-LABEL: movid:
222; CHECK: movi {{d[0-9]+}}, #0xff0000ff0000ffff
223	ret  <1 x i64> < i64 18374687574888349695 >
224}
225
226define <2 x float> @fmov2s() {
227; CHECK-LABEL: fmov2s:
228; CHECK:  fmov {{v[0-9]+}}.2s, #{{-12.00000000|-1.200000e\+01}}
229	ret <2 x float> < float -1.2e1, float -1.2e1>
230}
231
232define <4 x float> @fmov4s() {
233; CHECK-LABEL: fmov4s:
234; CHECK:  fmov {{v[0-9]+}}.4s, #{{-12.00000000|-1.200000e\+01}}
235	ret <4 x float> < float -1.2e1, float -1.2e1, float -1.2e1, float -1.2e1>
236}
237
238define <2 x double> @fmov2d() {
239; CHECK-LABEL: fmov2d:
240; CHECK:  fmov {{v[0-9]+}}.2d, #{{-12.00000000|-1.200000e\+01}}
241	ret <2 x double> < double -1.2e1, double -1.2e1>
242}
243
244define <2 x i32> @movi1d_1() {
245; CHECK-LABEL: movi1d_1:
246; CHECK: movi    d0, #0x{{0*}}ffffffff0000
247  ret <2 x i32> < i32  -65536, i32 65535>
248}
249
250
251declare <2 x i32> @test_movi1d(<2 x i32>, <2 x i32>)
252define <2 x i32> @movi1d() {
253; CHECK-LABEL: movi1d:
254; CHECK: adrp {{x[0-9]+}}, .{{[A-Z0-9_]+}}
255; CHECK: ldr {{d[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:.{{[A-Z0-9_]+}}]
256; CHECK-NEXT: movi     d1, #0x{{0*}}ffffffff0000
257  %1 = tail call <2 x i32> @test_movi1d(<2 x i32> <i32 -2147483648, i32 2147450880>, <2 x i32> <i32 -65536, i32 65535>)
258  ret <2 x i32> %1
259}
260
261