1; RUN: llc < %s -O3 -march=aarch64 -mcpu=cortex-a53 | FileCheck %s
2
3; With cortex-a53, each of fmul and fcvt have latency of 6 cycles.  After the
4; pre-RA MI scheduler, fmul, fcvt and fdiv will be consecutive.  The top-down
5; post-RA MI scheduler will clean this up.
6
7@d1 = common global double 0.000000e+00, align 8
8
9define i32 @test1(float %s2, float %s3, double %d, i32 %i2, i32 %i3) {
10entry:
11; CHECK-LABEL: @test1
12; CHECK: fmul
13; CHECK-NEXT: add
14; CHECK: fcvt
15; CHECK-NEXT: mul
16  %mul = fmul float %s2, %s3
17  %conv = fpext float %mul to double
18  %div = fdiv double %d, %conv
19  store double %div, double* @d1, align 8
20  %factor = shl i32 %i3, 1
21  %add1 = add i32 %i2, 4
22  %add2 = add i32 %add1, %factor
23  %add3 = add nsw i32 %add2, %i2
24  %add4 = add nsw i32 %add3, %add2
25  %mul5 = mul i32 %add3, %add3
26  %mul6 = mul i32 %mul5, %add4
27  %mul7 = shl i32 %add4, 1
28  %factor18 = mul i32 %mul7, %mul6
29  %add9 = add i32 %factor18, %mul6
30  ret i32 %add9
31}
32