1; RUN: llc < %s -asm-verbose=false -O3 -mtriple=armv6-apple-darwin -relocation-model=pic  -mcpu=arm1136jf-s -arm-atomic-cfg-tidy=0 | FileCheck %s
2; rdar://8959122 illegal register operands for UMULL instruction
3;   in cfrac nightly test.
4; Armv6 generates a umull that must write to two distinct destination regs.
5
6; ModuleID = 'bugpoint-reduced-simplified.bc'
7target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:32:64-v128:32:128-a0:0:64-n32"
8target triple = "armv6-apple-darwin10"
9
10define void @ptoa(i1 %tst, i8* %p8, i8 %val8) nounwind {
11entry:
12  br i1 false, label %bb3, label %bb
13
14bb:                                               ; preds = %entry
15  br label %bb3
16
17bb3:                                              ; preds = %bb, %entry
18  %0 = call noalias i8* @malloc() nounwind
19  br i1 %tst, label %bb46, label %bb8
20
21bb8:                                              ; preds = %bb3
22  %1 = getelementptr inbounds i8* %0, i32 0
23  store i8 0, i8* %1, align 1
24  %2 = call i32 @ptou() nounwind
25  ; CHECK: umull [[REGISTER:lr|r[0-9]+]],
26  ; CHECK-NOT: [[REGISTER]],
27  ; CHECK: {{lr|r[0-9]+}}, {{lr|r[0-9]+$}}
28  ; CHECK: umull [[REGISTER:lr|r[0-9]+]],
29  ; CHECK-NOT: [[REGISTER]],
30  ; CHECK: {{lr|r[0-9]+}}, {{lr|r[0-9]+$}}
31  %3 = udiv i32 %2, 10
32  %4 = urem i32 %3, 10
33  %5 = icmp ult i32 %4, 10
34  %6 = trunc i32 %4 to i8
35  %7 = or i8 %6, 48
36  %8 = add i8 %6, 87
37  %iftmp.5.0.1 = select i1 %5, i8 %7, i8 %8
38  store i8 %iftmp.5.0.1, i8* %p8, align 1
39  ; CHECK: umull [[REGISTER:lr|r[0-9]+]],
40  ; CHECK-NOT: [[REGISTER]],
41  ; CHECK: {{lr|r[0-9]+}}, {{lr|r[0-9]+$}}
42  ; CHECK: umull [[REGISTER:lr|r[0-9]+]],
43  ; CHECK-NOT: [[REGISTER]],
44  ; CHECK: {{lr|r[0-9]+}}, {{lr|r[0-9]+$}}
45  %9 = udiv i32 %2, 100
46  %10 = urem i32 %9, 10
47  %11 = icmp ult i32 %10, 10
48  %12 = trunc i32 %10 to i8
49  %13 = or i8 %12, 48
50  %14 = add i8 %12, 87
51  %iftmp.5.0.2 = select i1 %11, i8 %13, i8 %14
52  store i8 %iftmp.5.0.2, i8* %p8, align 1
53  ; CHECK: umull [[REGISTER:lr|r[0-9]+]],
54  ; CHECK-NOT: [[REGISTER]],
55  ; CHECK: {{lr|r[0-9]+}}, {{lr|r[0-9]+$}}
56  ; CHECK: umull [[REGISTER:lr|r[0-9]+]],
57  ; CHECK-NOT: [[REGISTER]],
58  ; CHECK: {{lr|r[0-9]+}}, {{lr|r[0-9]+$}}
59  %15 = udiv i32 %2, 10000
60  %16 = urem i32 %15, 10
61  %17 = icmp ult i32 %16, 10
62  %18 = trunc i32 %16 to i8
63  %19 = or i8 %18, 48
64  %20 = add i8 %18, 87
65  %iftmp.5.0.4 = select i1 %17, i8 %19, i8 %20
66  store i8 %iftmp.5.0.4, i8* null, align 1
67  ; CHECK: umull [[REGISTER:lr|r[0-9]+]],
68  ; CHECK-NOT: [[REGISTER]],
69  ; CHECK: {{lr|r[0-9]+}}, {{lr|r[0-9]+$}}
70  ; CHECK: umull [[REGISTER:lr|r[0-9]+]],
71  ; CHECK-NOT: [[REGISTER]],
72  ; CHECK: {{lr|r[0-9]+}}, {{lr|r[0-9]+$}}
73  %21 = udiv i32 %2, 100000
74  %22 = urem i32 %21, 10
75  %23 = icmp ult i32 %22, 10
76  %iftmp.5.0.5 = select i1 %23, i8 0, i8 %val8
77  store i8 %iftmp.5.0.5, i8* %p8, align 1
78  ; CHECK: umull [[REGISTER:lr|r[0-9]+]],
79  ; CHECK-NOT: [[REGISTER]],
80  ; CHECK: {{lr|r[0-9]+}}, {{lr|r[0-9]+$}}
81  ; CHECK: umull [[REGISTER:lr|r[0-9]+]],
82  ; CHECK-NOT: [[REGISTER]],
83  ; CHECK: {{lr|r[0-9]+}}, {{lr|r[0-9]+$}}
84  %24 = udiv i32 %2, 1000000
85  %25 = urem i32 %24, 10
86  %26 = icmp ult i32 %25, 10
87  %27 = trunc i32 %25 to i8
88  %28 = or i8 %27, 48
89  %29 = add i8 %27, 87
90  %iftmp.5.0.6 = select i1 %26, i8 %28, i8 %29
91  store i8 %iftmp.5.0.6, i8* %p8, align 1
92  ; CHECK: umull [[REGISTER:lr|r[0-9]+]],
93  ; CHECK-NOT: [[REGISTER]],
94  ; CHECK: {{lr|r[0-9]+}}, {{lr|r[0-9]+$}}
95  ; CHECK: umull [[REGISTER:lr|r[0-9]+]],
96  ; CHECK-NOT: [[REGISTER]],
97  ; CHECK: {{lr|r[0-9]+}}, {{lr|r[0-9]+$}}
98  %30 = udiv i32 %2, 10000000
99  %31 = urem i32 %30, 10
100  %32 = icmp ult i32 %31, 10
101  %33 = trunc i32 %31 to i8
102  %34 = or i8 %33, 48
103  %35 = add i8 %33, 87
104  %iftmp.5.0.7 = select i1 %32, i8 %34, i8 %35
105  store i8 %iftmp.5.0.7, i8* %p8, align 1
106  ; CHECK: umull [[REGISTER:lr|r[0-9]+]],
107  ; CHECK-NOT: [[REGISTER]],
108  ; CHECK: {{lr|r[0-9]+}}, {{lr|r[0-9]+$}}
109  ; CHECK: umull [[REGISTER:lr|r[0-9]+]],
110  ; CHECK-NOT: [[REGISTER]],
111  ; CHECK: {{lr|r[0-9]+}}, {{lr|r[0-9]+$}}
112  %36 = udiv i32 %2, 100000000
113  %37 = urem i32 %36, 10
114  %38 = icmp ult i32 %37, 10
115  %39 = trunc i32 %37 to i8
116  %40 = or i8 %39, 48
117  %41 = add i8 %39, 87
118  %iftmp.5.0.8 = select i1 %38, i8 %40, i8 %41
119  store i8 %iftmp.5.0.8, i8* null, align 1
120  br label %bb46
121
122bb46:                                             ; preds = %bb3
123  ret void
124}
125
126declare noalias i8* @malloc() nounwind
127
128declare i32 @ptou()
129