1; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB
2; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=pic -mtriple=arm-apple-ios | FileCheck %s --check-prefix=ARM
3; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARMv7
4; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=pic -mtriple=thumbv7-none-linux-gnueabi | FileCheck %s --check-prefix=THUMB-ELF
5; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=pic -mtriple=armv7-none-linux-gnueabi | FileCheck %s --check-prefix=ARMv7-ELF
6
7@g = global i32 0, align 4
8
9define i32 @LoadGV() {
10entry:
11; THUMB: LoadGV
12; THUMB: movw [[reg0:r[0-9]+]],
13; THUMB: movt [[reg0]],
14; THUMB: add  [[reg0]], pc
15; THUMB-ELF: LoadGV
16; THUMB-ELF: ldr r[[reg0:[0-9]+]],
17; THUMB-ELF: ldr r[[reg1:[0-9]+]],
18; THUMB-ELF: ldr r[[reg0]], [r[[reg0]], r[[reg1]]]
19; ARM: LoadGV
20; ARM: ldr [[reg1:r[0-9]+]],
21; ARM: add [[reg1]], pc, [[reg1]]
22; ARMv7: LoadGV
23; ARMv7: movw [[reg2:r[0-9]+]],
24; ARMv7: movt [[reg2]],
25; ARMv7: add  [[reg2]], pc, [[reg2]]
26; ARMv7-ELF: LoadGV
27; ARMv7-ELF: ldr r[[reg2:[0-9]+]],
28; ARMv7-ELF: .LPC
29; ARMv7-ELF-NEXT: add r[[reg2]], pc
30; ARMv7-ELF: ldr r[[reg3:[0-9]+]],
31; ARMv7-ELF: ldr r[[reg2]], [r[[reg3]], r[[reg2]]]
32  %tmp = load i32* @g
33  ret i32 %tmp
34}
35
36@i = external global i32
37
38define i32 @LoadIndirectSymbol() {
39entry:
40; THUMB: LoadIndirectSymbol
41; THUMB: movw r[[reg3:[0-9]+]],
42; THUMB: movt r[[reg3]],
43; THUMB: add  r[[reg3]], pc
44; THUMB: ldr  r[[reg3]], [r[[reg3]]]
45; THUMB-ELF: LoadIndirectSymbol
46; THUMB-ELF: ldr r[[reg3:[0-9]+]],
47; THUMB-ELF: ldr r[[reg4:[0-9]+]],
48; THUMB-ELF: ldr r[[reg3]], [r[[reg3]], r[[reg4]]]
49; ARM: LoadIndirectSymbol
50; ARM: ldr [[reg4:r[0-9]+]],
51; ARM: ldr [[reg4]], [pc, [[reg4]]]
52; ARMv7: LoadIndirectSymbol
53; ARMv7: movw r[[reg5:[0-9]+]],
54; ARMv7: movt r[[reg5]],
55; ARMv7: add  r[[reg5]], pc, r[[reg5]]
56; ARMv7: ldr  r[[reg5]], [r[[reg5]]]
57; ARMv7-ELF: LoadIndirectSymbol
58; ARMv7-ELF: ldr r[[reg5:[0-9]+]],
59; ARMv7-ELF: .LPC
60; ARMv7-ELF-NEXT: add r[[reg5]], pc
61; ARMv7-ELF: ldr r[[reg6:[0-9]+]],
62; ARMv7-ELF: ldr r[[reg5]], [r[[reg6]], r[[reg5]]]
63  %tmp = load i32* @i
64  ret i32 %tmp
65}
66