1; RUN: llc < %s -march=arm -mcpu=cortex-a8 -mattr=+vfp2 -enable-unsafe-fp-math | FileCheck %s
2; rdar://7461510
3; rdar://10964603
4
5; Disable this optimization unless we know one of them is zero.
6define arm_apcscc i32 @t1(float* %a, float* %b) nounwind {
7entry:
8; CHECK-LABEL: t1:
9; CHECK: vldr [[S0:s[0-9]+]],
10; CHECK: vldr [[S1:s[0-9]+]],
11; CHECK: vcmpe.f32 [[S1]], [[S0]]
12; CHECK: vmrs APSR_nzcv, fpscr
13; CHECK: beq
14  %0 = load float* %a
15  %1 = load float* %b
16  %2 = fcmp une float %0, %1
17  br i1 %2, label %bb1, label %bb2
18
19bb1:
20  %3 = call i32 @bar()
21  ret i32 %3
22
23bb2:
24  %4 = call i32 @foo()
25  ret i32 %4
26}
27
28; If one side is zero, the other size sign bit is masked off to allow
29; +0.0 == -0.0
30define arm_apcscc i32 @t2(double* %a, double* %b) nounwind {
31entry:
32; CHECK-LABEL: t2:
33; CHECK-NOT: vldr
34; CHECK: ldrd [[REG1:(r[0-9]+)]], [[REG2:(r[0-9]+)]], [r0]
35; CHECK-NOT: b LBB
36; CHECK: bfc [[REG2]], #31, #1
37; CHECK: cmp [[REG1]], #0
38; CHECK: cmpeq [[REG2]], #0
39; CHECK-NOT: vcmpe.f32
40; CHECK-NOT: vmrs
41; CHECK: bne
42  %0 = load double* %a
43  %1 = fcmp oeq double %0, 0.000000e+00
44  br i1 %1, label %bb1, label %bb2
45
46bb1:
47  %2 = call i32 @bar()
48  ret i32 %2
49
50bb2:
51  %3 = call i32 @foo()
52  ret i32 %3
53}
54
55define arm_apcscc i32 @t3(float* %a, float* %b) nounwind {
56entry:
57; CHECK-LABEL: t3:
58; CHECK-NOT: vldr
59; CHECK: ldr [[REG3:(r[0-9]+)]], [r0]
60; CHECK: mvn [[REG4:(r[0-9]+)]], #-2147483648
61; CHECK: tst [[REG3]], [[REG4]]
62; CHECK-NOT: vcmpe.f32
63; CHECK-NOT: vmrs
64; CHECK: bne
65  %0 = load float* %a
66  %1 = fcmp oeq float %0, 0.000000e+00
67  br i1 %1, label %bb1, label %bb2
68
69bb1:
70  %2 = call i32 @bar()
71  ret i32 %2
72
73bb2:
74  %3 = call i32 @foo()
75  ret i32 %3
76}
77
78declare i32 @bar()
79declare i32 @foo()
80