1; RUN: llc < %s -mtriple=thumbv7m-none-eabi -mcpu=cortex-m4 | FileCheck %s
2
3; CHECK-LABEL: f0:
4; CHECK-NOT: ldrexd
5define i64 @f0(i64* %p) nounwind readonly {
6entry:
7  %0 = load atomic i64* %p seq_cst, align 8
8  ret i64 %0
9}
10
11; CHECK-LABEL: f1:
12; CHECK-NOT: strexd
13define void @f1(i64* %p) nounwind readonly {
14entry:
15  store atomic i64 0, i64* %p seq_cst, align 8
16  ret void
17}
18
19; CHECK-LABEL: f2:
20; CHECK-NOT: ldrexd
21; CHECK-NOT: strexd
22define i64 @f2(i64* %p) nounwind readonly {
23entry:
24  %0 = atomicrmw add i64* %p, i64 1 seq_cst
25  ret i64 %0
26}
27
28; CHECK-LABEL: f3:
29; CHECK: ldr
30define i32 @f3(i32* %p) nounwind readonly {
31entry:
32  %0 = load atomic i32* %p seq_cst, align 4
33  ret i32 %0
34}
35
36; CHECK-LABEL: f4:
37; CHECK: ldrb
38define i8 @f4(i8* %p) nounwind readonly {
39entry:
40  %0 = load atomic i8* %p seq_cst, align 4
41  ret i8 %0
42}
43
44; CHECK-LABEL: f5:
45; CHECK: str
46define void @f5(i32* %p) nounwind readonly {
47entry:
48  store atomic i32 0, i32* %p seq_cst, align 4
49  ret void
50}
51
52; CHECK-LABEL: f6:
53; CHECK: ldrex
54; CHECK: strex
55define i32 @f6(i32* %p) nounwind readonly {
56entry:
57  %0 = atomicrmw add i32* %p, i32 1 seq_cst
58  ret i32 %0
59}
60