1; RUN: llc -mtriple=arm--none-eabi -mcpu=cortex-a8 %s -o - | FileCheck %s
2; RUN: llc -mtriple=thumb--none-eabi -mcpu=cortex-a8 %s -o - | FileCheck %s
3
4; We cannot codegen the smulw[bt] or smlaw[bt] instructions for these functions,
5; as the top 16 bits of the result would differ
6
7define i32 @f1(i32 %a, i16 %b) {
8; CHECK-LABEL: f1:
9; CHECK: mul
10; CHECK: asr
11  %tmp1 = sext i16 %b to i32
12  %tmp2 = mul i32 %a, %tmp1
13  %tmp3 = ashr i32 %tmp2, 16
14  ret i32 %tmp3
15}
16
17define i32 @f2(i32 %a, i16 %b, i32 %c) {
18; CHECK-LABEL: f2:
19; CHECK: mul
20; CHECK: add{{.*}}, asr #16
21  %tmp1 = sext i16 %b to i32
22  %tmp2 = mul i32 %a, %tmp1
23  %tmp3 = ashr i32 %tmp2, 16
24  %tmp4 = add i32 %tmp3, %c
25  ret i32 %tmp4
26}
27