1; RUN: llc -mtriple=armv7-apple-ios6.0 -mcpu=swift < %s | FileCheck %s
2; RUN: llc -mtriple=armv7-apple-ios6.0 < %s | FileCheck %s --check-prefix=CHECK-STRICT-ATOMIC
3
4; Release operations only need the store barrier provided by a "dmb ishst",
5
6define void @test_store_release(i32* %p, i32 %v) {
7; CHECK-LABEL: test_store_release:
8; CHECK: dmb ishst
9; CHECK: str
10
11; CHECK-STRICT-ATOMIC: dmb {{ish$}}
12  store atomic i32 %v, i32* %p release, align 4
13  ret void
14}
15
16; However, if sequential consistency is needed *something* must ensure a release
17; followed by an acquire does not get reordered. In that case a "dmb ishst" is
18; not adequate.
19define i32 @test_seq_cst(i32* %p, i32 %v) {
20; CHECK-LABEL: test_seq_cst:
21; CHECK: dmb ishst
22; CHECK: str
23; CHECK: dmb {{ish$}}
24; CHECK: ldr
25; CHECK: dmb {{ish$}}
26
27; CHECK-STRICT-ATOMIC: dmb {{ish$}}
28; CHECK-STRICT-ATOMIC: dmb {{ish$}}
29
30  store atomic i32 %v, i32* %p seq_cst, align 4
31  %val = load atomic i32* %p seq_cst, align 4
32  ret i32 %val
33}
34
35; Also, pure acquire operations should definitely not have an ishst barrier.
36
37define i32 @test_acq(i32* %addr) {
38; CHECK-LABEL: test_acq:
39; CHECK: ldr
40; CHECK: dmb {{ish$}}
41
42; CHECK-STRICT-ATOMIC: dmb {{ish$}}
43  %val = load atomic i32* %addr acquire, align 4
44  ret i32 %val
45}
46