1; RUN: llc < %s -mtriple armv8 -mattr=+neon | FileCheck %s 2; RUN: llc < %s -mtriple armv8 -mattr=+neon,+fp-armv8 -enable-unsafe-fp-math | FileCheck %s --check-prefix=CHECK-FAST 3 4define <4 x float> @vmaxnmq(<4 x float>* %A, <4 x float>* %B) nounwind { 5; CHECK-LABEL: vmaxnmq: 6; CHECK: vmaxnm.f32 q{{[0-9]+}}, q{{[0-9]+}}, q{{[0-9]+}} 7 %tmp1 = load <4 x float>* %A 8 %tmp2 = load <4 x float>* %B 9 %tmp3 = call <4 x float> @llvm.arm.neon.vmaxnm.v4f32(<4 x float> %tmp1, <4 x float> %tmp2) 10 ret <4 x float> %tmp3 11} 12 13define <2 x float> @vmaxnmd(<2 x float>* %A, <2 x float>* %B) nounwind { 14; CHECK-LABEL: vmaxnmd: 15; CHECK: vmaxnm.f32 d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}} 16 %tmp1 = load <2 x float>* %A 17 %tmp2 = load <2 x float>* %B 18 %tmp3 = call <2 x float> @llvm.arm.neon.vmaxnm.v2f32(<2 x float> %tmp1, <2 x float> %tmp2) 19 ret <2 x float> %tmp3 20} 21 22define <4 x float> @vminnmq(<4 x float>* %A, <4 x float>* %B) nounwind { 23; CHECK-LABEL: vminnmq: 24; CHECK: vminnm.f32 q{{[0-9]+}}, q{{[0-9]+}}, q{{[0-9]+}} 25 %tmp1 = load <4 x float>* %A 26 %tmp2 = load <4 x float>* %B 27 %tmp3 = call <4 x float> @llvm.arm.neon.vminnm.v4f32(<4 x float> %tmp1, <4 x float> %tmp2) 28 ret <4 x float> %tmp3 29} 30 31define <2 x float> @vminnmd(<2 x float>* %A, <2 x float>* %B) nounwind { 32; CHECK-LABEL: vminnmd: 33; CHECK: vminnm.f32 d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}} 34 %tmp1 = load <2 x float>* %A 35 %tmp2 = load <2 x float>* %B 36 %tmp3 = call <2 x float> @llvm.arm.neon.vminnm.v2f32(<2 x float> %tmp1, <2 x float> %tmp2) 37 ret <2 x float> %tmp3 38} 39 40define float @fp-armv8_vminnm_o(float %a, float %b) { 41; CHECK-FAST-LABEL: "fp-armv8_vminnm_o": 42; CHECK-FAST-NOT: vcmp 43; CHECK-FAST: vminnm.f32 44; CHECK-LABEL: "fp-armv8_vminnm_o": 45; CHECK-NOT: vminnm.f32 46 %cmp = fcmp olt float %a, %b 47 %cond = select i1 %cmp, float %a, float %b 48 ret float %cond 49} 50 51define float @fp-armv8_vminnm_o_rev(float %a, float %b) { 52; CHECK-FAST-LABEL: "fp-armv8_vminnm_o_rev": 53; CHECK-FAST-NOT: vcmp 54; CHECK-FAST: vminnm.f32 55; CHECK-LABEL: "fp-armv8_vminnm_o_rev": 56; CHECK-NOT: vminnm.f32 57 %cmp = fcmp ogt float %a, %b 58 %cond = select i1 %cmp, float %b, float %a 59 ret float %cond 60} 61 62define float @fp-armv8_vminnm_u(float %a, float %b) { 63; CHECK-FAST-LABEL: "fp-armv8_vminnm_u": 64; CHECK-FAST-NOT: vcmp 65; CHECK-FAST: vminnm.f32 66; CHECK-LABEL: "fp-armv8_vminnm_u": 67; CHECK-NOT: vminnm.f32 68 %cmp = fcmp ult float %a, %b 69 %cond = select i1 %cmp, float %a, float %b 70 ret float %cond 71} 72 73define float @fp-armv8_vminnm_u_rev(float %a, float %b) { 74; CHECK-FAST-LABEL: "fp-armv8_vminnm_u_rev": 75; CHECK-FAST-NOT: vcmp 76; CHECK-FAST: vminnm.f32 77; CHECK-LABEL: "fp-armv8_vminnm_u_rev": 78; CHECK-NOT: vminnm.f32 79 %cmp = fcmp ugt float %a, %b 80 %cond = select i1 %cmp, float %b, float %a 81 ret float %cond 82} 83 84define float @fp-armv8_vmaxnm_o(float %a, float %b) { 85; CHECK-FAST-LABEL: "fp-armv8_vmaxnm_o": 86; CHECK-FAST-NOT: vcmp 87; CHECK-FAST: vmaxnm.f32 88; CHECK-LABEL: "fp-armv8_vmaxnm_o": 89; CHECK-NOT: vmaxnm.f32 90 %cmp = fcmp ogt float %a, %b 91 %cond = select i1 %cmp, float %a, float %b 92 ret float %cond 93} 94 95define float @fp-armv8_vmaxnm_o_rev(float %a, float %b) { 96; CHECK-FAST-LABEL: "fp-armv8_vmaxnm_o_rev": 97; CHECK-FAST-NOT: vcmp 98; CHECK-FAST: vmaxnm.f32 99; CHECK-LABEL: "fp-armv8_vmaxnm_o_rev": 100; CHECK-NOT: vmaxnm.f32 101 %cmp = fcmp olt float %a, %b 102 %cond = select i1 %cmp, float %b, float %a 103 ret float %cond 104} 105 106define float @fp-armv8_vmaxnm_u(float %a, float %b) { 107; CHECK-FAST-LABEL: "fp-armv8_vmaxnm_u": 108; CHECK-FAST-NOT: vcmp 109; CHECK-FAST: vmaxnm.f32 110; CHECK-LABEL: "fp-armv8_vmaxnm_u": 111; CHECK-NOT: vmaxnm.f32 112 %cmp = fcmp ugt float %a, %b 113 %cond = select i1 %cmp, float %a, float %b 114 ret float %cond 115} 116 117define float @fp-armv8_vmaxnm_u_rev(float %a, float %b) { 118; CHECK-FAST-LABEL: "fp-armv8_vmaxnm_u_rev": 119; CHECK-FAST-NOT: vcmp 120; CHECK-FAST: vmaxnm.f32 121; CHECK-LABEL: "fp-armv8_vmaxnm_u_rev": 122; CHECK-NOT: vmaxnm.f32 123 %cmp = fcmp ult float %a, %b 124 %cond = select i1 %cmp, float %b, float %a 125 ret float %cond 126} 127 128 129declare <4 x float> @llvm.arm.neon.vminnm.v4f32(<4 x float>, <4 x float>) nounwind readnone 130declare <2 x float> @llvm.arm.neon.vminnm.v2f32(<2 x float>, <2 x float>) nounwind readnone 131declare <4 x float> @llvm.arm.neon.vmaxnm.v4f32(<4 x float>, <4 x float>) nounwind readnone 132declare <2 x float> @llvm.arm.neon.vmaxnm.v2f32(<2 x float>, <2 x float>) nounwind readnone 133