1; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s
2; Check that we generate compare to predicate register.
3
4define i32 @compare1(i32 %a, i32 %b) nounwind {
5; CHECK: p{{[0-3]}}{{ *}}={{ *}}!cmp.eq(r{{[0-9]+}},{{ *}}r{{[0-9]+}})
6entry:
7  %cmp = icmp ne i32 %a, %b
8  %add = add nsw i32 %a, %b
9  %sub = sub nsw i32 %a, %b
10  %add.sub = select i1 %cmp, i32 %add, i32 %sub
11  ret i32 %add.sub
12}
13
14define i32 @compare2(i32 %a) nounwind {
15; CHECK: p{{[0-3]}}{{ *}}={{ *}}!cmp.eq(r{{[0-9]+}},{{ *}}#10)
16entry:
17  %cmp = icmp ne i32 %a, 10
18  %add = add nsw i32 %a, 10
19  %sub = sub nsw i32 %a, 10
20  %add.sub = select i1 %cmp, i32 %add, i32 %sub
21  ret i32 %add.sub
22}
23
24define i32 @compare3(i32 %a, i32 %b) nounwind {
25; CHECK: p{{[0-3]}}{{ *}}={{ *}}cmp.gt(r{{[0-9]+}},{{ *}}r{{[0-9]+}})
26entry:
27  %cmp = icmp sgt i32 %a, %b
28  %sub = sub nsw i32 %a, %b
29  %add = add nsw i32 %a, %b
30  %sub.add = select i1 %cmp, i32 %sub, i32 %add
31  ret i32 %sub.add
32}
33
34define i32 @compare4(i32 %a) nounwind {
35; CHECK: p{{[0-3]}}{{ *}}={{ *}}cmp.gt(r{{[0-9]+}},{{ *}}#10)
36entry:
37  %cmp = icmp sgt i32 %a, 10
38  %sub = sub nsw i32 %a, 10
39  %add = add nsw i32 %a, 10
40  %sub.add = select i1 %cmp, i32 %sub, i32 %add
41  ret i32 %sub.add
42}
43
44