1; RUN: llc -march=hexagon -mcpu=hexagonv5  < %s | FileCheck %s
2; Generate various cmpb instruction followed by if (p0) .. if (!p0)...
3target triple = "hexagon"
4
5@Enum_global = external global i8
6
7define i32 @Func_3(i32) nounwind readnone {
8entry:
9; CHECK-NOT: mux
10  %conv = and i32 %0, 255
11  %cmp = icmp eq i32 %conv, 2
12  %selv = zext i1 %cmp to i32
13  ret i32 %selv
14}
15
16define i32 @Func_3b(i32) nounwind readonly {
17entry:
18; CHECK-NOT: mux
19  %1 = load i8* @Enum_global, align 1
20  %2 = trunc i32 %0 to i8
21  %cmp = icmp ne i8 %1, %2
22  %selv = zext i1 %cmp to i32
23  ret i32 %selv
24}
25
26define i32 @Func_3c(i32) nounwind readnone {
27entry:
28; CHECK-NOT: mux
29  %conv = and i32 %0, 255
30  %cmp = icmp eq i32 %conv, 2
31  %selv = zext i1 %cmp to i32
32  ret i32 %selv
33}
34
35define i32 @Func_3d(i32) nounwind readonly {
36entry:
37; CHECK-NOT: mux
38  %1 = load i8* @Enum_global, align 1
39  %2 = trunc i32 %0 to i8
40  %cmp = icmp eq i8 %1, %2
41  %selv = zext i1 %cmp to i32
42  ret i32 %selv
43}
44
45define i32 @Func_3e(i32) nounwind readonly {
46entry:
47; CHECK-NOT: mux
48  %1 = load i8* @Enum_global, align 1
49  %2 = trunc i32 %0 to i8
50  %cmp = icmp eq i8 %1, %2
51  %selv = zext i1 %cmp to i32
52  ret i32 %selv
53}
54
55define i32 @Func_3f(i32) nounwind readnone {
56entry:
57; CHECK-NOT: mux
58  %conv = and i32 %0, 255
59  %cmp = icmp ugt i32 %conv, 2
60  %selv = zext i1 %cmp to i32
61  ret i32 %selv
62}
63
64define i32 @Func_3g(i32) nounwind readnone {
65entry:
66; CHECK: mux
67  %conv = and i32 %0, 255
68  %cmp = icmp ult i32 %conv, 3
69  %selv = zext i1 %cmp to i32
70  ret i32 %selv
71}
72
73define i32 @Func_3h(i32) nounwind readnone {
74entry:
75; CHECK-NOT: mux
76  %conv = and i32 %0, 254
77  %cmp = icmp ult i32 %conv, 2
78  %selv = zext i1 %cmp to i32
79  ret i32 %selv
80}
81
82define i32 @Func_3i(i32) nounwind readnone {
83entry:
84; CHECK-NOT: mux
85  %conv = and i32 %0, 254
86  %cmp = icmp ugt i32 %conv, 1
87  %selv = zext i1 %cmp to i32
88  ret i32 %selv
89}
90