1; RUN: llc -march=hexagon -mcpu=hexagonv4  < %s | FileCheck %s
2; Check that we generate fused logical and with shift instruction.
3
4; CHECK: r{{[0-9]+}} = and(#15, lsr(r{{[0-9]+}}, #{{[0-9]+}})
5
6define i32 @main(i16* %a, i16* %b) nounwind {
7  entry:
8  %0 = load i16* %a, align 2
9  %conv1 = sext i16 %0 to i32
10  %shr1 = ashr i32 %conv1, 3
11  %and1 = and i32 %shr1, 15
12  %conv2 = trunc i32 %and1 to i16
13  store i16 %conv2, i16* %b, align 2
14  ret i32 0
15}
16
17