1; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s 2; Generate MemOps for V4 and above. 3 4define void @memop_unsigned_char_add5(i8* nocapture %p) nounwind { 5entry: 6; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}#5 7 %0 = load i8* %p, align 1 8 %conv = zext i8 %0 to i32 9 %add = add nsw i32 %conv, 5 10 %conv1 = trunc i32 %add to i8 11 store i8 %conv1, i8* %p, align 1 12 ret void 13} 14 15define void @memop_unsigned_char_add(i8* nocapture %p, i8 zeroext %x) nounwind { 16entry: 17; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}r{{[0-9]+}} 18 %conv = zext i8 %x to i32 19 %0 = load i8* %p, align 1 20 %conv1 = zext i8 %0 to i32 21 %add = add nsw i32 %conv1, %conv 22 %conv2 = trunc i32 %add to i8 23 store i8 %conv2, i8* %p, align 1 24 ret void 25} 26 27define void @memop_unsigned_char_sub(i8* nocapture %p, i8 zeroext %x) nounwind { 28entry: 29; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}-={{ *}}r{{[0-9]+}} 30 %conv = zext i8 %x to i32 31 %0 = load i8* %p, align 1 32 %conv1 = zext i8 %0 to i32 33 %sub = sub nsw i32 %conv1, %conv 34 %conv2 = trunc i32 %sub to i8 35 store i8 %conv2, i8* %p, align 1 36 ret void 37} 38 39define void @memop_unsigned_char_or(i8* nocapture %p, i8 zeroext %x) nounwind { 40entry: 41; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}|={{ *}}r{{[0-9]+}} 42 %0 = load i8* %p, align 1 43 %or3 = or i8 %0, %x 44 store i8 %or3, i8* %p, align 1 45 ret void 46} 47 48define void @memop_unsigned_char_and(i8* nocapture %p, i8 zeroext %x) nounwind { 49entry: 50; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}&={{ *}}r{{[0-9]+}} 51 %0 = load i8* %p, align 1 52 %and3 = and i8 %0, %x 53 store i8 %and3, i8* %p, align 1 54 ret void 55} 56 57define void @memop_unsigned_char_clrbit(i8* nocapture %p) nounwind { 58entry: 59; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}clrbit({{ *}}#5{{ *}}) 60 %0 = load i8* %p, align 1 61 %conv = zext i8 %0 to i32 62 %and = and i32 %conv, 223 63 %conv1 = trunc i32 %and to i8 64 store i8 %conv1, i8* %p, align 1 65 ret void 66} 67 68define void @memop_unsigned_char_setbit(i8* nocapture %p) nounwind { 69entry: 70; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}setbit({{ *}}#7{{ *}}) 71 %0 = load i8* %p, align 1 72 %conv = zext i8 %0 to i32 73 %or = or i32 %conv, 128 74 %conv1 = trunc i32 %or to i8 75 store i8 %conv1, i8* %p, align 1 76 ret void 77} 78 79define void @memop_unsigned_char_add5_index(i8* nocapture %p, i32 %i) nounwind { 80entry: 81; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}#5 82 %add.ptr = getelementptr inbounds i8* %p, i32 %i 83 %0 = load i8* %add.ptr, align 1 84 %conv = zext i8 %0 to i32 85 %add = add nsw i32 %conv, 5 86 %conv1 = trunc i32 %add to i8 87 store i8 %conv1, i8* %add.ptr, align 1 88 ret void 89} 90 91define void @memop_unsigned_char_add_index(i8* nocapture %p, i32 %i, i8 zeroext %x) nounwind { 92entry: 93; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}r{{[0-9]+}} 94 %conv = zext i8 %x to i32 95 %add.ptr = getelementptr inbounds i8* %p, i32 %i 96 %0 = load i8* %add.ptr, align 1 97 %conv1 = zext i8 %0 to i32 98 %add = add nsw i32 %conv1, %conv 99 %conv2 = trunc i32 %add to i8 100 store i8 %conv2, i8* %add.ptr, align 1 101 ret void 102} 103 104define void @memop_unsigned_char_sub_index(i8* nocapture %p, i32 %i, i8 zeroext %x) nounwind { 105entry: 106; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}-={{ *}}r{{[0-9]+}} 107 %conv = zext i8 %x to i32 108 %add.ptr = getelementptr inbounds i8* %p, i32 %i 109 %0 = load i8* %add.ptr, align 1 110 %conv1 = zext i8 %0 to i32 111 %sub = sub nsw i32 %conv1, %conv 112 %conv2 = trunc i32 %sub to i8 113 store i8 %conv2, i8* %add.ptr, align 1 114 ret void 115} 116 117define void @memop_unsigned_char_or_index(i8* nocapture %p, i32 %i, i8 zeroext %x) nounwind { 118entry: 119; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}|={{ *}}r{{[0-9]+}} 120 %add.ptr = getelementptr inbounds i8* %p, i32 %i 121 %0 = load i8* %add.ptr, align 1 122 %or3 = or i8 %0, %x 123 store i8 %or3, i8* %add.ptr, align 1 124 ret void 125} 126 127define void @memop_unsigned_char_and_index(i8* nocapture %p, i32 %i, i8 zeroext %x) nounwind { 128entry: 129; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}&={{ *}}r{{[0-9]+}} 130 %add.ptr = getelementptr inbounds i8* %p, i32 %i 131 %0 = load i8* %add.ptr, align 1 132 %and3 = and i8 %0, %x 133 store i8 %and3, i8* %add.ptr, align 1 134 ret void 135} 136 137define void @memop_unsigned_char_clrbit_index(i8* nocapture %p, i32 %i) nounwind { 138entry: 139; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}clrbit({{ *}}#5{{ *}}) 140 %add.ptr = getelementptr inbounds i8* %p, i32 %i 141 %0 = load i8* %add.ptr, align 1 142 %conv = zext i8 %0 to i32 143 %and = and i32 %conv, 223 144 %conv1 = trunc i32 %and to i8 145 store i8 %conv1, i8* %add.ptr, align 1 146 ret void 147} 148 149define void @memop_unsigned_char_setbit_index(i8* nocapture %p, i32 %i) nounwind { 150entry: 151; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}setbit({{ *}}#7{{ *}}) 152 %add.ptr = getelementptr inbounds i8* %p, i32 %i 153 %0 = load i8* %add.ptr, align 1 154 %conv = zext i8 %0 to i32 155 %or = or i32 %conv, 128 156 %conv1 = trunc i32 %or to i8 157 store i8 %conv1, i8* %add.ptr, align 1 158 ret void 159} 160 161define void @memop_unsigned_char_add5_index5(i8* nocapture %p) nounwind { 162entry: 163; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#5){{ *}}+={{ *}}#5 164 %add.ptr = getelementptr inbounds i8* %p, i32 5 165 %0 = load i8* %add.ptr, align 1 166 %conv = zext i8 %0 to i32 167 %add = add nsw i32 %conv, 5 168 %conv1 = trunc i32 %add to i8 169 store i8 %conv1, i8* %add.ptr, align 1 170 ret void 171} 172 173define void @memop_unsigned_char_add_index5(i8* nocapture %p, i8 zeroext %x) nounwind { 174entry: 175; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#5){{ *}}+={{ *}}r{{[0-9]+}} 176 %conv = zext i8 %x to i32 177 %add.ptr = getelementptr inbounds i8* %p, i32 5 178 %0 = load i8* %add.ptr, align 1 179 %conv1 = zext i8 %0 to i32 180 %add = add nsw i32 %conv1, %conv 181 %conv2 = trunc i32 %add to i8 182 store i8 %conv2, i8* %add.ptr, align 1 183 ret void 184} 185 186define void @memop_unsigned_char_sub_index5(i8* nocapture %p, i8 zeroext %x) nounwind { 187entry: 188; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#5){{ *}}-={{ *}}r{{[0-9]+}} 189 %conv = zext i8 %x to i32 190 %add.ptr = getelementptr inbounds i8* %p, i32 5 191 %0 = load i8* %add.ptr, align 1 192 %conv1 = zext i8 %0 to i32 193 %sub = sub nsw i32 %conv1, %conv 194 %conv2 = trunc i32 %sub to i8 195 store i8 %conv2, i8* %add.ptr, align 1 196 ret void 197} 198 199define void @memop_unsigned_char_or_index5(i8* nocapture %p, i8 zeroext %x) nounwind { 200entry: 201; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#5){{ *}}|={{ *}}r{{[0-9]+}} 202 %add.ptr = getelementptr inbounds i8* %p, i32 5 203 %0 = load i8* %add.ptr, align 1 204 %or3 = or i8 %0, %x 205 store i8 %or3, i8* %add.ptr, align 1 206 ret void 207} 208 209define void @memop_unsigned_char_and_index5(i8* nocapture %p, i8 zeroext %x) nounwind { 210entry: 211; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#5){{ *}}&={{ *}}r{{[0-9]+}} 212 %add.ptr = getelementptr inbounds i8* %p, i32 5 213 %0 = load i8* %add.ptr, align 1 214 %and3 = and i8 %0, %x 215 store i8 %and3, i8* %add.ptr, align 1 216 ret void 217} 218 219define void @memop_unsigned_char_clrbit_index5(i8* nocapture %p) nounwind { 220entry: 221; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#5){{ *}}={{ *}}clrbit({{ *}}#5{{ *}}) 222 %add.ptr = getelementptr inbounds i8* %p, i32 5 223 %0 = load i8* %add.ptr, align 1 224 %conv = zext i8 %0 to i32 225 %and = and i32 %conv, 223 226 %conv1 = trunc i32 %and to i8 227 store i8 %conv1, i8* %add.ptr, align 1 228 ret void 229} 230 231define void @memop_unsigned_char_setbit_index5(i8* nocapture %p) nounwind { 232entry: 233; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#5){{ *}}={{ *}}setbit({{ *}}#7{{ *}}) 234 %add.ptr = getelementptr inbounds i8* %p, i32 5 235 %0 = load i8* %add.ptr, align 1 236 %conv = zext i8 %0 to i32 237 %or = or i32 %conv, 128 238 %conv1 = trunc i32 %or to i8 239 store i8 %conv1, i8* %add.ptr, align 1 240 ret void 241} 242 243define void @memop_signed_char_add5(i8* nocapture %p) nounwind { 244entry: 245; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}#5 246 %0 = load i8* %p, align 1 247 %conv2 = zext i8 %0 to i32 248 %add = add nsw i32 %conv2, 5 249 %conv1 = trunc i32 %add to i8 250 store i8 %conv1, i8* %p, align 1 251 ret void 252} 253 254define void @memop_signed_char_add(i8* nocapture %p, i8 signext %x) nounwind { 255entry: 256; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}r{{[0-9]+}} 257 %conv4 = zext i8 %x to i32 258 %0 = load i8* %p, align 1 259 %conv13 = zext i8 %0 to i32 260 %add = add nsw i32 %conv13, %conv4 261 %conv2 = trunc i32 %add to i8 262 store i8 %conv2, i8* %p, align 1 263 ret void 264} 265 266define void @memop_signed_char_sub(i8* nocapture %p, i8 signext %x) nounwind { 267entry: 268; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}-={{ *}}r{{[0-9]+}} 269 %conv4 = zext i8 %x to i32 270 %0 = load i8* %p, align 1 271 %conv13 = zext i8 %0 to i32 272 %sub = sub nsw i32 %conv13, %conv4 273 %conv2 = trunc i32 %sub to i8 274 store i8 %conv2, i8* %p, align 1 275 ret void 276} 277 278define void @memop_signed_char_or(i8* nocapture %p, i8 signext %x) nounwind { 279entry: 280; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}|={{ *}}r{{[0-9]+}} 281 %0 = load i8* %p, align 1 282 %or3 = or i8 %0, %x 283 store i8 %or3, i8* %p, align 1 284 ret void 285} 286 287define void @memop_signed_char_and(i8* nocapture %p, i8 signext %x) nounwind { 288entry: 289; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}&={{ *}}r{{[0-9]+}} 290 %0 = load i8* %p, align 1 291 %and3 = and i8 %0, %x 292 store i8 %and3, i8* %p, align 1 293 ret void 294} 295 296define void @memop_signed_char_clrbit(i8* nocapture %p) nounwind { 297entry: 298; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}clrbit({{ *}}#5{{ *}}) 299 %0 = load i8* %p, align 1 300 %conv2 = zext i8 %0 to i32 301 %and = and i32 %conv2, 223 302 %conv1 = trunc i32 %and to i8 303 store i8 %conv1, i8* %p, align 1 304 ret void 305} 306 307define void @memop_signed_char_setbit(i8* nocapture %p) nounwind { 308entry: 309; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}setbit({{ *}}#7{{ *}}) 310 %0 = load i8* %p, align 1 311 %conv2 = zext i8 %0 to i32 312 %or = or i32 %conv2, 128 313 %conv1 = trunc i32 %or to i8 314 store i8 %conv1, i8* %p, align 1 315 ret void 316} 317 318define void @memop_signed_char_add5_index(i8* nocapture %p, i32 %i) nounwind { 319entry: 320; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}#5 321 %add.ptr = getelementptr inbounds i8* %p, i32 %i 322 %0 = load i8* %add.ptr, align 1 323 %conv2 = zext i8 %0 to i32 324 %add = add nsw i32 %conv2, 5 325 %conv1 = trunc i32 %add to i8 326 store i8 %conv1, i8* %add.ptr, align 1 327 ret void 328} 329 330define void @memop_signed_char_add_index(i8* nocapture %p, i32 %i, i8 signext %x) nounwind { 331entry: 332; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}r{{[0-9]+}} 333 %conv4 = zext i8 %x to i32 334 %add.ptr = getelementptr inbounds i8* %p, i32 %i 335 %0 = load i8* %add.ptr, align 1 336 %conv13 = zext i8 %0 to i32 337 %add = add nsw i32 %conv13, %conv4 338 %conv2 = trunc i32 %add to i8 339 store i8 %conv2, i8* %add.ptr, align 1 340 ret void 341} 342 343define void @memop_signed_char_sub_index(i8* nocapture %p, i32 %i, i8 signext %x) nounwind { 344entry: 345; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}-={{ *}}r{{[0-9]+}} 346 %conv4 = zext i8 %x to i32 347 %add.ptr = getelementptr inbounds i8* %p, i32 %i 348 %0 = load i8* %add.ptr, align 1 349 %conv13 = zext i8 %0 to i32 350 %sub = sub nsw i32 %conv13, %conv4 351 %conv2 = trunc i32 %sub to i8 352 store i8 %conv2, i8* %add.ptr, align 1 353 ret void 354} 355 356define void @memop_signed_char_or_index(i8* nocapture %p, i32 %i, i8 signext %x) nounwind { 357entry: 358; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}|={{ *}}r{{[0-9]+}} 359 %add.ptr = getelementptr inbounds i8* %p, i32 %i 360 %0 = load i8* %add.ptr, align 1 361 %or3 = or i8 %0, %x 362 store i8 %or3, i8* %add.ptr, align 1 363 ret void 364} 365 366define void @memop_signed_char_and_index(i8* nocapture %p, i32 %i, i8 signext %x) nounwind { 367entry: 368; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}&={{ *}}r{{[0-9]+}} 369 %add.ptr = getelementptr inbounds i8* %p, i32 %i 370 %0 = load i8* %add.ptr, align 1 371 %and3 = and i8 %0, %x 372 store i8 %and3, i8* %add.ptr, align 1 373 ret void 374} 375 376define void @memop_signed_char_clrbit_index(i8* nocapture %p, i32 %i) nounwind { 377entry: 378; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}clrbit({{ *}}#5{{ *}}) 379 %add.ptr = getelementptr inbounds i8* %p, i32 %i 380 %0 = load i8* %add.ptr, align 1 381 %conv2 = zext i8 %0 to i32 382 %and = and i32 %conv2, 223 383 %conv1 = trunc i32 %and to i8 384 store i8 %conv1, i8* %add.ptr, align 1 385 ret void 386} 387 388define void @memop_signed_char_setbit_index(i8* nocapture %p, i32 %i) nounwind { 389entry: 390; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}setbit({{ *}}#7{{ *}}) 391 %add.ptr = getelementptr inbounds i8* %p, i32 %i 392 %0 = load i8* %add.ptr, align 1 393 %conv2 = zext i8 %0 to i32 394 %or = or i32 %conv2, 128 395 %conv1 = trunc i32 %or to i8 396 store i8 %conv1, i8* %add.ptr, align 1 397 ret void 398} 399 400define void @memop_signed_char_add5_index5(i8* nocapture %p) nounwind { 401entry: 402; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#5){{ *}}+={{ *}}#5 403 %add.ptr = getelementptr inbounds i8* %p, i32 5 404 %0 = load i8* %add.ptr, align 1 405 %conv2 = zext i8 %0 to i32 406 %add = add nsw i32 %conv2, 5 407 %conv1 = trunc i32 %add to i8 408 store i8 %conv1, i8* %add.ptr, align 1 409 ret void 410} 411 412define void @memop_signed_char_add_index5(i8* nocapture %p, i8 signext %x) nounwind { 413entry: 414; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#5){{ *}}+={{ *}}r{{[0-9]+}} 415 %conv4 = zext i8 %x to i32 416 %add.ptr = getelementptr inbounds i8* %p, i32 5 417 %0 = load i8* %add.ptr, align 1 418 %conv13 = zext i8 %0 to i32 419 %add = add nsw i32 %conv13, %conv4 420 %conv2 = trunc i32 %add to i8 421 store i8 %conv2, i8* %add.ptr, align 1 422 ret void 423} 424 425define void @memop_signed_char_sub_index5(i8* nocapture %p, i8 signext %x) nounwind { 426entry: 427; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#5){{ *}}-={{ *}}r{{[0-9]+}} 428 %conv4 = zext i8 %x to i32 429 %add.ptr = getelementptr inbounds i8* %p, i32 5 430 %0 = load i8* %add.ptr, align 1 431 %conv13 = zext i8 %0 to i32 432 %sub = sub nsw i32 %conv13, %conv4 433 %conv2 = trunc i32 %sub to i8 434 store i8 %conv2, i8* %add.ptr, align 1 435 ret void 436} 437 438define void @memop_signed_char_or_index5(i8* nocapture %p, i8 signext %x) nounwind { 439entry: 440; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#5){{ *}}|={{ *}}r{{[0-9]+}} 441 %add.ptr = getelementptr inbounds i8* %p, i32 5 442 %0 = load i8* %add.ptr, align 1 443 %or3 = or i8 %0, %x 444 store i8 %or3, i8* %add.ptr, align 1 445 ret void 446} 447 448define void @memop_signed_char_and_index5(i8* nocapture %p, i8 signext %x) nounwind { 449entry: 450; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#5){{ *}}&={{ *}}r{{[0-9]+}} 451 %add.ptr = getelementptr inbounds i8* %p, i32 5 452 %0 = load i8* %add.ptr, align 1 453 %and3 = and i8 %0, %x 454 store i8 %and3, i8* %add.ptr, align 1 455 ret void 456} 457 458define void @memop_signed_char_clrbit_index5(i8* nocapture %p) nounwind { 459entry: 460; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#5){{ *}}={{ *}}clrbit({{ *}}#5{{ *}}) 461 %add.ptr = getelementptr inbounds i8* %p, i32 5 462 %0 = load i8* %add.ptr, align 1 463 %conv2 = zext i8 %0 to i32 464 %and = and i32 %conv2, 223 465 %conv1 = trunc i32 %and to i8 466 store i8 %conv1, i8* %add.ptr, align 1 467 ret void 468} 469 470define void @memop_signed_char_setbit_index5(i8* nocapture %p) nounwind { 471entry: 472; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#5){{ *}}={{ *}}setbit({{ *}}#7{{ *}}) 473 %add.ptr = getelementptr inbounds i8* %p, i32 5 474 %0 = load i8* %add.ptr, align 1 475 %conv2 = zext i8 %0 to i32 476 %or = or i32 %conv2, 128 477 %conv1 = trunc i32 %or to i8 478 store i8 %conv1, i8* %add.ptr, align 1 479 ret void 480} 481 482define void @memop_unsigned_short_add5(i16* nocapture %p) nounwind { 483entry: 484; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}#5 485 %0 = load i16* %p, align 2 486 %conv = zext i16 %0 to i32 487 %add = add nsw i32 %conv, 5 488 %conv1 = trunc i32 %add to i16 489 store i16 %conv1, i16* %p, align 2 490 ret void 491} 492 493define void @memop_unsigned_short_add(i16* nocapture %p, i16 zeroext %x) nounwind { 494entry: 495; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}r{{[0-9]+}} 496 %conv = zext i16 %x to i32 497 %0 = load i16* %p, align 2 498 %conv1 = zext i16 %0 to i32 499 %add = add nsw i32 %conv1, %conv 500 %conv2 = trunc i32 %add to i16 501 store i16 %conv2, i16* %p, align 2 502 ret void 503} 504 505define void @memop_unsigned_short_sub(i16* nocapture %p, i16 zeroext %x) nounwind { 506entry: 507; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}-={{ *}}r{{[0-9]+}} 508 %conv = zext i16 %x to i32 509 %0 = load i16* %p, align 2 510 %conv1 = zext i16 %0 to i32 511 %sub = sub nsw i32 %conv1, %conv 512 %conv2 = trunc i32 %sub to i16 513 store i16 %conv2, i16* %p, align 2 514 ret void 515} 516 517define void @memop_unsigned_short_or(i16* nocapture %p, i16 zeroext %x) nounwind { 518entry: 519; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}|={{ *}}r{{[0-9]+}} 520 %0 = load i16* %p, align 2 521 %or3 = or i16 %0, %x 522 store i16 %or3, i16* %p, align 2 523 ret void 524} 525 526define void @memop_unsigned_short_and(i16* nocapture %p, i16 zeroext %x) nounwind { 527entry: 528; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}&={{ *}}r{{[0-9]+}} 529 %0 = load i16* %p, align 2 530 %and3 = and i16 %0, %x 531 store i16 %and3, i16* %p, align 2 532 ret void 533} 534 535define void @memop_unsigned_short_clrbit(i16* nocapture %p) nounwind { 536entry: 537; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}clrbit({{ *}}#5{{ *}}) 538 %0 = load i16* %p, align 2 539 %conv = zext i16 %0 to i32 540 %and = and i32 %conv, 65503 541 %conv1 = trunc i32 %and to i16 542 store i16 %conv1, i16* %p, align 2 543 ret void 544} 545 546define void @memop_unsigned_short_setbit(i16* nocapture %p) nounwind { 547entry: 548; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}setbit({{ *}}#7{{ *}}) 549 %0 = load i16* %p, align 2 550 %conv = zext i16 %0 to i32 551 %or = or i32 %conv, 128 552 %conv1 = trunc i32 %or to i16 553 store i16 %conv1, i16* %p, align 2 554 ret void 555} 556 557define void @memop_unsigned_short_add5_index(i16* nocapture %p, i32 %i) nounwind { 558entry: 559; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}#5 560 %add.ptr = getelementptr inbounds i16* %p, i32 %i 561 %0 = load i16* %add.ptr, align 2 562 %conv = zext i16 %0 to i32 563 %add = add nsw i32 %conv, 5 564 %conv1 = trunc i32 %add to i16 565 store i16 %conv1, i16* %add.ptr, align 2 566 ret void 567} 568 569define void @memop_unsigned_short_add_index(i16* nocapture %p, i32 %i, i16 zeroext %x) nounwind { 570entry: 571; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}r{{[0-9]+}} 572 %conv = zext i16 %x to i32 573 %add.ptr = getelementptr inbounds i16* %p, i32 %i 574 %0 = load i16* %add.ptr, align 2 575 %conv1 = zext i16 %0 to i32 576 %add = add nsw i32 %conv1, %conv 577 %conv2 = trunc i32 %add to i16 578 store i16 %conv2, i16* %add.ptr, align 2 579 ret void 580} 581 582define void @memop_unsigned_short_sub_index(i16* nocapture %p, i32 %i, i16 zeroext %x) nounwind { 583entry: 584; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}-={{ *}}r{{[0-9]+}} 585 %conv = zext i16 %x to i32 586 %add.ptr = getelementptr inbounds i16* %p, i32 %i 587 %0 = load i16* %add.ptr, align 2 588 %conv1 = zext i16 %0 to i32 589 %sub = sub nsw i32 %conv1, %conv 590 %conv2 = trunc i32 %sub to i16 591 store i16 %conv2, i16* %add.ptr, align 2 592 ret void 593} 594 595define void @memop_unsigned_short_or_index(i16* nocapture %p, i32 %i, i16 zeroext %x) nounwind { 596entry: 597; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}|={{ *}}r{{[0-9]+}} 598 %add.ptr = getelementptr inbounds i16* %p, i32 %i 599 %0 = load i16* %add.ptr, align 2 600 %or3 = or i16 %0, %x 601 store i16 %or3, i16* %add.ptr, align 2 602 ret void 603} 604 605define void @memop_unsigned_short_and_index(i16* nocapture %p, i32 %i, i16 zeroext %x) nounwind { 606entry: 607; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}&={{ *}}r{{[0-9]+}} 608 %add.ptr = getelementptr inbounds i16* %p, i32 %i 609 %0 = load i16* %add.ptr, align 2 610 %and3 = and i16 %0, %x 611 store i16 %and3, i16* %add.ptr, align 2 612 ret void 613} 614 615define void @memop_unsigned_short_clrbit_index(i16* nocapture %p, i32 %i) nounwind { 616entry: 617; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}clrbit({{ *}}#5{{ *}}) 618 %add.ptr = getelementptr inbounds i16* %p, i32 %i 619 %0 = load i16* %add.ptr, align 2 620 %conv = zext i16 %0 to i32 621 %and = and i32 %conv, 65503 622 %conv1 = trunc i32 %and to i16 623 store i16 %conv1, i16* %add.ptr, align 2 624 ret void 625} 626 627define void @memop_unsigned_short_setbit_index(i16* nocapture %p, i32 %i) nounwind { 628entry: 629; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}setbit({{ *}}#7{{ *}}) 630 %add.ptr = getelementptr inbounds i16* %p, i32 %i 631 %0 = load i16* %add.ptr, align 2 632 %conv = zext i16 %0 to i32 633 %or = or i32 %conv, 128 634 %conv1 = trunc i32 %or to i16 635 store i16 %conv1, i16* %add.ptr, align 2 636 ret void 637} 638 639define void @memop_unsigned_short_add5_index5(i16* nocapture %p) nounwind { 640entry: 641; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}+={{ *}}#5 642 %add.ptr = getelementptr inbounds i16* %p, i32 5 643 %0 = load i16* %add.ptr, align 2 644 %conv = zext i16 %0 to i32 645 %add = add nsw i32 %conv, 5 646 %conv1 = trunc i32 %add to i16 647 store i16 %conv1, i16* %add.ptr, align 2 648 ret void 649} 650 651define void @memop_unsigned_short_add_index5(i16* nocapture %p, i16 zeroext %x) nounwind { 652entry: 653; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}+={{ *}}r{{[0-9]+}} 654 %conv = zext i16 %x to i32 655 %add.ptr = getelementptr inbounds i16* %p, i32 5 656 %0 = load i16* %add.ptr, align 2 657 %conv1 = zext i16 %0 to i32 658 %add = add nsw i32 %conv1, %conv 659 %conv2 = trunc i32 %add to i16 660 store i16 %conv2, i16* %add.ptr, align 2 661 ret void 662} 663 664define void @memop_unsigned_short_sub_index5(i16* nocapture %p, i16 zeroext %x) nounwind { 665entry: 666; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}-={{ *}}r{{[0-9]+}} 667 %conv = zext i16 %x to i32 668 %add.ptr = getelementptr inbounds i16* %p, i32 5 669 %0 = load i16* %add.ptr, align 2 670 %conv1 = zext i16 %0 to i32 671 %sub = sub nsw i32 %conv1, %conv 672 %conv2 = trunc i32 %sub to i16 673 store i16 %conv2, i16* %add.ptr, align 2 674 ret void 675} 676 677define void @memop_unsigned_short_or_index5(i16* nocapture %p, i16 zeroext %x) nounwind { 678entry: 679; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}|={{ *}}r{{[0-9]+}} 680 %add.ptr = getelementptr inbounds i16* %p, i32 5 681 %0 = load i16* %add.ptr, align 2 682 %or3 = or i16 %0, %x 683 store i16 %or3, i16* %add.ptr, align 2 684 ret void 685} 686 687define void @memop_unsigned_short_and_index5(i16* nocapture %p, i16 zeroext %x) nounwind { 688entry: 689; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}&={{ *}}r{{[0-9]+}} 690 %add.ptr = getelementptr inbounds i16* %p, i32 5 691 %0 = load i16* %add.ptr, align 2 692 %and3 = and i16 %0, %x 693 store i16 %and3, i16* %add.ptr, align 2 694 ret void 695} 696 697define void @memop_unsigned_short_clrbit_index5(i16* nocapture %p) nounwind { 698entry: 699; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}={{ *}}clrbit({{ *}}#5{{ *}}) 700 %add.ptr = getelementptr inbounds i16* %p, i32 5 701 %0 = load i16* %add.ptr, align 2 702 %conv = zext i16 %0 to i32 703 %and = and i32 %conv, 65503 704 %conv1 = trunc i32 %and to i16 705 store i16 %conv1, i16* %add.ptr, align 2 706 ret void 707} 708 709define void @memop_unsigned_short_setbit_index5(i16* nocapture %p) nounwind { 710entry: 711; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}={{ *}}setbit({{ *}}#7{{ *}}) 712 %add.ptr = getelementptr inbounds i16* %p, i32 5 713 %0 = load i16* %add.ptr, align 2 714 %conv = zext i16 %0 to i32 715 %or = or i32 %conv, 128 716 %conv1 = trunc i32 %or to i16 717 store i16 %conv1, i16* %add.ptr, align 2 718 ret void 719} 720 721define void @memop_signed_short_add5(i16* nocapture %p) nounwind { 722entry: 723; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}#5 724 %0 = load i16* %p, align 2 725 %conv2 = zext i16 %0 to i32 726 %add = add nsw i32 %conv2, 5 727 %conv1 = trunc i32 %add to i16 728 store i16 %conv1, i16* %p, align 2 729 ret void 730} 731 732define void @memop_signed_short_add(i16* nocapture %p, i16 signext %x) nounwind { 733entry: 734; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}r{{[0-9]+}} 735 %conv4 = zext i16 %x to i32 736 %0 = load i16* %p, align 2 737 %conv13 = zext i16 %0 to i32 738 %add = add nsw i32 %conv13, %conv4 739 %conv2 = trunc i32 %add to i16 740 store i16 %conv2, i16* %p, align 2 741 ret void 742} 743 744define void @memop_signed_short_sub(i16* nocapture %p, i16 signext %x) nounwind { 745entry: 746; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}-={{ *}}r{{[0-9]+}} 747 %conv4 = zext i16 %x to i32 748 %0 = load i16* %p, align 2 749 %conv13 = zext i16 %0 to i32 750 %sub = sub nsw i32 %conv13, %conv4 751 %conv2 = trunc i32 %sub to i16 752 store i16 %conv2, i16* %p, align 2 753 ret void 754} 755 756define void @memop_signed_short_or(i16* nocapture %p, i16 signext %x) nounwind { 757entry: 758; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}|={{ *}}r{{[0-9]+}} 759 %0 = load i16* %p, align 2 760 %or3 = or i16 %0, %x 761 store i16 %or3, i16* %p, align 2 762 ret void 763} 764 765define void @memop_signed_short_and(i16* nocapture %p, i16 signext %x) nounwind { 766entry: 767; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}&={{ *}}r{{[0-9]+}} 768 %0 = load i16* %p, align 2 769 %and3 = and i16 %0, %x 770 store i16 %and3, i16* %p, align 2 771 ret void 772} 773 774define void @memop_signed_short_clrbit(i16* nocapture %p) nounwind { 775entry: 776; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}clrbit({{ *}}#5{{ *}}) 777 %0 = load i16* %p, align 2 778 %conv2 = zext i16 %0 to i32 779 %and = and i32 %conv2, 65503 780 %conv1 = trunc i32 %and to i16 781 store i16 %conv1, i16* %p, align 2 782 ret void 783} 784 785define void @memop_signed_short_setbit(i16* nocapture %p) nounwind { 786entry: 787; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}setbit({{ *}}#7{{ *}}) 788 %0 = load i16* %p, align 2 789 %conv2 = zext i16 %0 to i32 790 %or = or i32 %conv2, 128 791 %conv1 = trunc i32 %or to i16 792 store i16 %conv1, i16* %p, align 2 793 ret void 794} 795 796define void @memop_signed_short_add5_index(i16* nocapture %p, i32 %i) nounwind { 797entry: 798; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}#5 799 %add.ptr = getelementptr inbounds i16* %p, i32 %i 800 %0 = load i16* %add.ptr, align 2 801 %conv2 = zext i16 %0 to i32 802 %add = add nsw i32 %conv2, 5 803 %conv1 = trunc i32 %add to i16 804 store i16 %conv1, i16* %add.ptr, align 2 805 ret void 806} 807 808define void @memop_signed_short_add_index(i16* nocapture %p, i32 %i, i16 signext %x) nounwind { 809entry: 810; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}r{{[0-9]+}} 811 %conv4 = zext i16 %x to i32 812 %add.ptr = getelementptr inbounds i16* %p, i32 %i 813 %0 = load i16* %add.ptr, align 2 814 %conv13 = zext i16 %0 to i32 815 %add = add nsw i32 %conv13, %conv4 816 %conv2 = trunc i32 %add to i16 817 store i16 %conv2, i16* %add.ptr, align 2 818 ret void 819} 820 821define void @memop_signed_short_sub_index(i16* nocapture %p, i32 %i, i16 signext %x) nounwind { 822entry: 823; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}-={{ *}}r{{[0-9]+}} 824 %conv4 = zext i16 %x to i32 825 %add.ptr = getelementptr inbounds i16* %p, i32 %i 826 %0 = load i16* %add.ptr, align 2 827 %conv13 = zext i16 %0 to i32 828 %sub = sub nsw i32 %conv13, %conv4 829 %conv2 = trunc i32 %sub to i16 830 store i16 %conv2, i16* %add.ptr, align 2 831 ret void 832} 833 834define void @memop_signed_short_or_index(i16* nocapture %p, i32 %i, i16 signext %x) nounwind { 835entry: 836; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}|={{ *}}r{{[0-9]+}} 837 %add.ptr = getelementptr inbounds i16* %p, i32 %i 838 %0 = load i16* %add.ptr, align 2 839 %or3 = or i16 %0, %x 840 store i16 %or3, i16* %add.ptr, align 2 841 ret void 842} 843 844define void @memop_signed_short_and_index(i16* nocapture %p, i32 %i, i16 signext %x) nounwind { 845entry: 846; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}&={{ *}}r{{[0-9]+}} 847 %add.ptr = getelementptr inbounds i16* %p, i32 %i 848 %0 = load i16* %add.ptr, align 2 849 %and3 = and i16 %0, %x 850 store i16 %and3, i16* %add.ptr, align 2 851 ret void 852} 853 854define void @memop_signed_short_clrbit_index(i16* nocapture %p, i32 %i) nounwind { 855entry: 856; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}clrbit({{ *}}#5{{ *}}) 857 %add.ptr = getelementptr inbounds i16* %p, i32 %i 858 %0 = load i16* %add.ptr, align 2 859 %conv2 = zext i16 %0 to i32 860 %and = and i32 %conv2, 65503 861 %conv1 = trunc i32 %and to i16 862 store i16 %conv1, i16* %add.ptr, align 2 863 ret void 864} 865 866define void @memop_signed_short_setbit_index(i16* nocapture %p, i32 %i) nounwind { 867entry: 868; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}setbit({{ *}}#7{{ *}}) 869 %add.ptr = getelementptr inbounds i16* %p, i32 %i 870 %0 = load i16* %add.ptr, align 2 871 %conv2 = zext i16 %0 to i32 872 %or = or i32 %conv2, 128 873 %conv1 = trunc i32 %or to i16 874 store i16 %conv1, i16* %add.ptr, align 2 875 ret void 876} 877 878define void @memop_signed_short_add5_index5(i16* nocapture %p) nounwind { 879entry: 880; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}+={{ *}}#5 881 %add.ptr = getelementptr inbounds i16* %p, i32 5 882 %0 = load i16* %add.ptr, align 2 883 %conv2 = zext i16 %0 to i32 884 %add = add nsw i32 %conv2, 5 885 %conv1 = trunc i32 %add to i16 886 store i16 %conv1, i16* %add.ptr, align 2 887 ret void 888} 889 890define void @memop_signed_short_add_index5(i16* nocapture %p, i16 signext %x) nounwind { 891entry: 892; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}+={{ *}}r{{[0-9]+}} 893 %conv4 = zext i16 %x to i32 894 %add.ptr = getelementptr inbounds i16* %p, i32 5 895 %0 = load i16* %add.ptr, align 2 896 %conv13 = zext i16 %0 to i32 897 %add = add nsw i32 %conv13, %conv4 898 %conv2 = trunc i32 %add to i16 899 store i16 %conv2, i16* %add.ptr, align 2 900 ret void 901} 902 903define void @memop_signed_short_sub_index5(i16* nocapture %p, i16 signext %x) nounwind { 904entry: 905; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}-={{ *}}r{{[0-9]+}} 906 %conv4 = zext i16 %x to i32 907 %add.ptr = getelementptr inbounds i16* %p, i32 5 908 %0 = load i16* %add.ptr, align 2 909 %conv13 = zext i16 %0 to i32 910 %sub = sub nsw i32 %conv13, %conv4 911 %conv2 = trunc i32 %sub to i16 912 store i16 %conv2, i16* %add.ptr, align 2 913 ret void 914} 915 916define void @memop_signed_short_or_index5(i16* nocapture %p, i16 signext %x) nounwind { 917entry: 918; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}|={{ *}}r{{[0-9]+}} 919 %add.ptr = getelementptr inbounds i16* %p, i32 5 920 %0 = load i16* %add.ptr, align 2 921 %or3 = or i16 %0, %x 922 store i16 %or3, i16* %add.ptr, align 2 923 ret void 924} 925 926define void @memop_signed_short_and_index5(i16* nocapture %p, i16 signext %x) nounwind { 927entry: 928; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}&={{ *}}r{{[0-9]+}} 929 %add.ptr = getelementptr inbounds i16* %p, i32 5 930 %0 = load i16* %add.ptr, align 2 931 %and3 = and i16 %0, %x 932 store i16 %and3, i16* %add.ptr, align 2 933 ret void 934} 935 936define void @memop_signed_short_clrbit_index5(i16* nocapture %p) nounwind { 937entry: 938; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}={{ *}}clrbit({{ *}}#5{{ *}}) 939 %add.ptr = getelementptr inbounds i16* %p, i32 5 940 %0 = load i16* %add.ptr, align 2 941 %conv2 = zext i16 %0 to i32 942 %and = and i32 %conv2, 65503 943 %conv1 = trunc i32 %and to i16 944 store i16 %conv1, i16* %add.ptr, align 2 945 ret void 946} 947 948define void @memop_signed_short_setbit_index5(i16* nocapture %p) nounwind { 949entry: 950; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}={{ *}}setbit({{ *}}#7{{ *}}) 951 %add.ptr = getelementptr inbounds i16* %p, i32 5 952 %0 = load i16* %add.ptr, align 2 953 %conv2 = zext i16 %0 to i32 954 %or = or i32 %conv2, 128 955 %conv1 = trunc i32 %or to i16 956 store i16 %conv1, i16* %add.ptr, align 2 957 ret void 958} 959 960define void @memop_signed_int_add5(i32* nocapture %p) nounwind { 961entry: 962; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}#5 963 %0 = load i32* %p, align 4 964 %add = add i32 %0, 5 965 store i32 %add, i32* %p, align 4 966 ret void 967} 968 969define void @memop_signed_int_add(i32* nocapture %p, i32 %x) nounwind { 970entry: 971; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}r{{[0-9]+}} 972 %0 = load i32* %p, align 4 973 %add = add i32 %0, %x 974 store i32 %add, i32* %p, align 4 975 ret void 976} 977 978define void @memop_signed_int_sub(i32* nocapture %p, i32 %x) nounwind { 979entry: 980; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}-={{ *}}r{{[0-9]+}} 981 %0 = load i32* %p, align 4 982 %sub = sub i32 %0, %x 983 store i32 %sub, i32* %p, align 4 984 ret void 985} 986 987define void @memop_signed_int_or(i32* nocapture %p, i32 %x) nounwind { 988entry: 989; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}|={{ *}}r{{[0-9]+}} 990 %0 = load i32* %p, align 4 991 %or = or i32 %0, %x 992 store i32 %or, i32* %p, align 4 993 ret void 994} 995 996define void @memop_signed_int_and(i32* nocapture %p, i32 %x) nounwind { 997entry: 998; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}&={{ *}}r{{[0-9]+}} 999 %0 = load i32* %p, align 4 1000 %and = and i32 %0, %x 1001 store i32 %and, i32* %p, align 4 1002 ret void 1003} 1004 1005define void @memop_signed_int_clrbit(i32* nocapture %p) nounwind { 1006entry: 1007; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}clrbit({{ *}}#5{{ *}}) 1008 %0 = load i32* %p, align 4 1009 %and = and i32 %0, -33 1010 store i32 %and, i32* %p, align 4 1011 ret void 1012} 1013 1014define void @memop_signed_int_setbit(i32* nocapture %p) nounwind { 1015entry: 1016; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}setbit({{ *}}#7{{ *}}) 1017 %0 = load i32* %p, align 4 1018 %or = or i32 %0, 128 1019 store i32 %or, i32* %p, align 4 1020 ret void 1021} 1022 1023define void @memop_signed_int_add5_index(i32* nocapture %p, i32 %i) nounwind { 1024entry: 1025; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}#5 1026 %add.ptr = getelementptr inbounds i32* %p, i32 %i 1027 %0 = load i32* %add.ptr, align 4 1028 %add = add i32 %0, 5 1029 store i32 %add, i32* %add.ptr, align 4 1030 ret void 1031} 1032 1033define void @memop_signed_int_add_index(i32* nocapture %p, i32 %i, i32 %x) nounwind { 1034entry: 1035; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}r{{[0-9]+}} 1036 %add.ptr = getelementptr inbounds i32* %p, i32 %i 1037 %0 = load i32* %add.ptr, align 4 1038 %add = add i32 %0, %x 1039 store i32 %add, i32* %add.ptr, align 4 1040 ret void 1041} 1042 1043define void @memop_signed_int_sub_index(i32* nocapture %p, i32 %i, i32 %x) nounwind { 1044entry: 1045; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}-={{ *}}r{{[0-9]+}} 1046 %add.ptr = getelementptr inbounds i32* %p, i32 %i 1047 %0 = load i32* %add.ptr, align 4 1048 %sub = sub i32 %0, %x 1049 store i32 %sub, i32* %add.ptr, align 4 1050 ret void 1051} 1052 1053define void @memop_signed_int_or_index(i32* nocapture %p, i32 %i, i32 %x) nounwind { 1054entry: 1055; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}|={{ *}}r{{[0-9]+}} 1056 %add.ptr = getelementptr inbounds i32* %p, i32 %i 1057 %0 = load i32* %add.ptr, align 4 1058 %or = or i32 %0, %x 1059 store i32 %or, i32* %add.ptr, align 4 1060 ret void 1061} 1062 1063define void @memop_signed_int_and_index(i32* nocapture %p, i32 %i, i32 %x) nounwind { 1064entry: 1065; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}&={{ *}}r{{[0-9]+}} 1066 %add.ptr = getelementptr inbounds i32* %p, i32 %i 1067 %0 = load i32* %add.ptr, align 4 1068 %and = and i32 %0, %x 1069 store i32 %and, i32* %add.ptr, align 4 1070 ret void 1071} 1072 1073define void @memop_signed_int_clrbit_index(i32* nocapture %p, i32 %i) nounwind { 1074entry: 1075; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}clrbit({{ *}}#5{{ *}}) 1076 %add.ptr = getelementptr inbounds i32* %p, i32 %i 1077 %0 = load i32* %add.ptr, align 4 1078 %and = and i32 %0, -33 1079 store i32 %and, i32* %add.ptr, align 4 1080 ret void 1081} 1082 1083define void @memop_signed_int_setbit_index(i32* nocapture %p, i32 %i) nounwind { 1084entry: 1085; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}setbit({{ *}}#7{{ *}}) 1086 %add.ptr = getelementptr inbounds i32* %p, i32 %i 1087 %0 = load i32* %add.ptr, align 4 1088 %or = or i32 %0, 128 1089 store i32 %or, i32* %add.ptr, align 4 1090 ret void 1091} 1092 1093define void @memop_signed_int_add5_index5(i32* nocapture %p) nounwind { 1094entry: 1095; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}+={{ *}}#5 1096 %add.ptr = getelementptr inbounds i32* %p, i32 5 1097 %0 = load i32* %add.ptr, align 4 1098 %add = add i32 %0, 5 1099 store i32 %add, i32* %add.ptr, align 4 1100 ret void 1101} 1102 1103define void @memop_signed_int_add_index5(i32* nocapture %p, i32 %x) nounwind { 1104entry: 1105; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}+={{ *}}r{{[0-9]+}} 1106 %add.ptr = getelementptr inbounds i32* %p, i32 5 1107 %0 = load i32* %add.ptr, align 4 1108 %add = add i32 %0, %x 1109 store i32 %add, i32* %add.ptr, align 4 1110 ret void 1111} 1112 1113define void @memop_signed_int_sub_index5(i32* nocapture %p, i32 %x) nounwind { 1114entry: 1115; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}-={{ *}}r{{[0-9]+}} 1116 %add.ptr = getelementptr inbounds i32* %p, i32 5 1117 %0 = load i32* %add.ptr, align 4 1118 %sub = sub i32 %0, %x 1119 store i32 %sub, i32* %add.ptr, align 4 1120 ret void 1121} 1122 1123define void @memop_signed_int_or_index5(i32* nocapture %p, i32 %x) nounwind { 1124entry: 1125; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}|={{ *}}r{{[0-9]+}} 1126 %add.ptr = getelementptr inbounds i32* %p, i32 5 1127 %0 = load i32* %add.ptr, align 4 1128 %or = or i32 %0, %x 1129 store i32 %or, i32* %add.ptr, align 4 1130 ret void 1131} 1132 1133define void @memop_signed_int_and_index5(i32* nocapture %p, i32 %x) nounwind { 1134entry: 1135; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}&={{ *}}r{{[0-9]+}} 1136 %add.ptr = getelementptr inbounds i32* %p, i32 5 1137 %0 = load i32* %add.ptr, align 4 1138 %and = and i32 %0, %x 1139 store i32 %and, i32* %add.ptr, align 4 1140 ret void 1141} 1142 1143define void @memop_signed_int_clrbit_index5(i32* nocapture %p) nounwind { 1144entry: 1145; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}={{ *}}clrbit({{ *}}#5{{ *}}) 1146 %add.ptr = getelementptr inbounds i32* %p, i32 5 1147 %0 = load i32* %add.ptr, align 4 1148 %and = and i32 %0, -33 1149 store i32 %and, i32* %add.ptr, align 4 1150 ret void 1151} 1152 1153define void @memop_signed_int_setbit_index5(i32* nocapture %p) nounwind { 1154entry: 1155; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}={{ *}}setbit({{ *}}#7{{ *}}) 1156 %add.ptr = getelementptr inbounds i32* %p, i32 5 1157 %0 = load i32* %add.ptr, align 4 1158 %or = or i32 %0, 128 1159 store i32 %or, i32* %add.ptr, align 4 1160 ret void 1161} 1162 1163define void @memop_unsigned_int_add5(i32* nocapture %p) nounwind { 1164entry: 1165; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}#5 1166 %0 = load i32* %p, align 4 1167 %add = add nsw i32 %0, 5 1168 store i32 %add, i32* %p, align 4 1169 ret void 1170} 1171 1172define void @memop_unsigned_int_add(i32* nocapture %p, i32 %x) nounwind { 1173entry: 1174; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}r{{[0-9]+}} 1175 %0 = load i32* %p, align 4 1176 %add = add nsw i32 %0, %x 1177 store i32 %add, i32* %p, align 4 1178 ret void 1179} 1180 1181define void @memop_unsigned_int_sub(i32* nocapture %p, i32 %x) nounwind { 1182entry: 1183; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}-={{ *}}r{{[0-9]+}} 1184 %0 = load i32* %p, align 4 1185 %sub = sub nsw i32 %0, %x 1186 store i32 %sub, i32* %p, align 4 1187 ret void 1188} 1189 1190define void @memop_unsigned_int_or(i32* nocapture %p, i32 %x) nounwind { 1191entry: 1192; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}|={{ *}}r{{[0-9]+}} 1193 %0 = load i32* %p, align 4 1194 %or = or i32 %0, %x 1195 store i32 %or, i32* %p, align 4 1196 ret void 1197} 1198 1199define void @memop_unsigned_int_and(i32* nocapture %p, i32 %x) nounwind { 1200entry: 1201; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}&={{ *}}r{{[0-9]+}} 1202 %0 = load i32* %p, align 4 1203 %and = and i32 %0, %x 1204 store i32 %and, i32* %p, align 4 1205 ret void 1206} 1207 1208define void @memop_unsigned_int_clrbit(i32* nocapture %p) nounwind { 1209entry: 1210; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}clrbit({{ *}}#5{{ *}}) 1211 %0 = load i32* %p, align 4 1212 %and = and i32 %0, -33 1213 store i32 %and, i32* %p, align 4 1214 ret void 1215} 1216 1217define void @memop_unsigned_int_setbit(i32* nocapture %p) nounwind { 1218entry: 1219; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}setbit({{ *}}#7{{ *}}) 1220 %0 = load i32* %p, align 4 1221 %or = or i32 %0, 128 1222 store i32 %or, i32* %p, align 4 1223 ret void 1224} 1225 1226define void @memop_unsigned_int_add5_index(i32* nocapture %p, i32 %i) nounwind { 1227entry: 1228; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}#5 1229 %add.ptr = getelementptr inbounds i32* %p, i32 %i 1230 %0 = load i32* %add.ptr, align 4 1231 %add = add nsw i32 %0, 5 1232 store i32 %add, i32* %add.ptr, align 4 1233 ret void 1234} 1235 1236define void @memop_unsigned_int_add_index(i32* nocapture %p, i32 %i, i32 %x) nounwind { 1237entry: 1238; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}r{{[0-9]+}} 1239 %add.ptr = getelementptr inbounds i32* %p, i32 %i 1240 %0 = load i32* %add.ptr, align 4 1241 %add = add nsw i32 %0, %x 1242 store i32 %add, i32* %add.ptr, align 4 1243 ret void 1244} 1245 1246define void @memop_unsigned_int_sub_index(i32* nocapture %p, i32 %i, i32 %x) nounwind { 1247entry: 1248; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}-={{ *}}r{{[0-9]+}} 1249 %add.ptr = getelementptr inbounds i32* %p, i32 %i 1250 %0 = load i32* %add.ptr, align 4 1251 %sub = sub nsw i32 %0, %x 1252 store i32 %sub, i32* %add.ptr, align 4 1253 ret void 1254} 1255 1256define void @memop_unsigned_int_or_index(i32* nocapture %p, i32 %i, i32 %x) nounwind { 1257entry: 1258; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}|={{ *}}r{{[0-9]+}} 1259 %add.ptr = getelementptr inbounds i32* %p, i32 %i 1260 %0 = load i32* %add.ptr, align 4 1261 %or = or i32 %0, %x 1262 store i32 %or, i32* %add.ptr, align 4 1263 ret void 1264} 1265 1266define void @memop_unsigned_int_and_index(i32* nocapture %p, i32 %i, i32 %x) nounwind { 1267entry: 1268; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}&={{ *}}r{{[0-9]+}} 1269 %add.ptr = getelementptr inbounds i32* %p, i32 %i 1270 %0 = load i32* %add.ptr, align 4 1271 %and = and i32 %0, %x 1272 store i32 %and, i32* %add.ptr, align 4 1273 ret void 1274} 1275 1276define void @memop_unsigned_int_clrbit_index(i32* nocapture %p, i32 %i) nounwind { 1277entry: 1278; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}clrbit({{ *}}#5{{ *}}) 1279 %add.ptr = getelementptr inbounds i32* %p, i32 %i 1280 %0 = load i32* %add.ptr, align 4 1281 %and = and i32 %0, -33 1282 store i32 %and, i32* %add.ptr, align 4 1283 ret void 1284} 1285 1286define void @memop_unsigned_int_setbit_index(i32* nocapture %p, i32 %i) nounwind { 1287entry: 1288; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}setbit({{ *}}#7{{ *}}) 1289 %add.ptr = getelementptr inbounds i32* %p, i32 %i 1290 %0 = load i32* %add.ptr, align 4 1291 %or = or i32 %0, 128 1292 store i32 %or, i32* %add.ptr, align 4 1293 ret void 1294} 1295 1296define void @memop_unsigned_int_add5_index5(i32* nocapture %p) nounwind { 1297entry: 1298; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}+={{ *}}#5 1299 %add.ptr = getelementptr inbounds i32* %p, i32 5 1300 %0 = load i32* %add.ptr, align 4 1301 %add = add nsw i32 %0, 5 1302 store i32 %add, i32* %add.ptr, align 4 1303 ret void 1304} 1305 1306define void @memop_unsigned_int_add_index5(i32* nocapture %p, i32 %x) nounwind { 1307entry: 1308; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}+={{ *}}r{{[0-9]+}} 1309 %add.ptr = getelementptr inbounds i32* %p, i32 5 1310 %0 = load i32* %add.ptr, align 4 1311 %add = add nsw i32 %0, %x 1312 store i32 %add, i32* %add.ptr, align 4 1313 ret void 1314} 1315 1316define void @memop_unsigned_int_sub_index5(i32* nocapture %p, i32 %x) nounwind { 1317entry: 1318; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}-={{ *}}r{{[0-9]+}} 1319 %add.ptr = getelementptr inbounds i32* %p, i32 5 1320 %0 = load i32* %add.ptr, align 4 1321 %sub = sub nsw i32 %0, %x 1322 store i32 %sub, i32* %add.ptr, align 4 1323 ret void 1324} 1325 1326define void @memop_unsigned_int_or_index5(i32* nocapture %p, i32 %x) nounwind { 1327entry: 1328; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}|={{ *}}r{{[0-9]+}} 1329 %add.ptr = getelementptr inbounds i32* %p, i32 5 1330 %0 = load i32* %add.ptr, align 4 1331 %or = or i32 %0, %x 1332 store i32 %or, i32* %add.ptr, align 4 1333 ret void 1334} 1335 1336define void @memop_unsigned_int_and_index5(i32* nocapture %p, i32 %x) nounwind { 1337entry: 1338; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}&={{ *}}r{{[0-9]+}} 1339 %add.ptr = getelementptr inbounds i32* %p, i32 5 1340 %0 = load i32* %add.ptr, align 4 1341 %and = and i32 %0, %x 1342 store i32 %and, i32* %add.ptr, align 4 1343 ret void 1344} 1345 1346define void @memop_unsigned_int_clrbit_index5(i32* nocapture %p) nounwind { 1347entry: 1348; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}={{ *}}clrbit({{ *}}#5{{ *}}) 1349 %add.ptr = getelementptr inbounds i32* %p, i32 5 1350 %0 = load i32* %add.ptr, align 4 1351 %and = and i32 %0, -33 1352 store i32 %and, i32* %add.ptr, align 4 1353 ret void 1354} 1355 1356define void @memop_unsigned_int_setbit_index5(i32* nocapture %p) nounwind { 1357entry: 1358; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}={{ *}}setbit({{ *}}#7{{ *}}) 1359 %add.ptr = getelementptr inbounds i32* %p, i32 5 1360 %0 = load i32* %add.ptr, align 4 1361 %or = or i32 %0, 128 1362 store i32 %or, i32* %add.ptr, align 4 1363 ret void 1364} 1365