1; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s
2
3; Check that post-increment store instructions are being generated.
4; CHECK: memw(r{{[0-9]+}}{{ *}}++{{ *}}#4{{ *}}){{ *}}={{ *}}r{{[0-9]+}}
5
6define i32 @sum(i32* nocapture %a, i16* nocapture %b, i32 %n) nounwind {
7entry:
8  br label %for.body
9
10for.body:                                         ; preds = %for.body, %entry
11  %lsr.iv = phi i32 [ %lsr.iv.next, %for.body ], [ 10, %entry ]
12  %arrayidx.phi = phi i32* [ %a, %entry ], [ %arrayidx.inc, %for.body ]
13  %arrayidx1.phi = phi i16* [ %b, %entry ], [ %arrayidx1.inc, %for.body ]
14  %0 = load i32* %arrayidx.phi, align 4
15  %1 = load i16* %arrayidx1.phi, align 2
16  %conv = sext i16 %1 to i32
17  %factor = mul i32 %0, 2
18  %add3 = add i32 %factor, %conv
19  store i32 %add3, i32* %arrayidx.phi, align 4
20
21  %arrayidx.inc = getelementptr i32* %arrayidx.phi, i32 1
22  %arrayidx1.inc = getelementptr i16* %arrayidx1.phi, i32 1
23  %lsr.iv.next = add i32 %lsr.iv, -1
24  %exitcond = icmp eq i32 %lsr.iv.next, 0
25  br i1 %exitcond, label %for.end, label %for.body
26
27for.end:                                          ; preds = %for.body
28  ret i32 0
29}
30