1; RUN: llc -march=mips < %s | FileCheck %s
2; RUN: llc -march=mips64el -mcpu=mips64r2 -mattr=n64 < %s | FileCheck %s
3
4%struct.DWstruct = type { i32, i32 }
5
6define i32 @A0(i32 %u, i32 %v) nounwind  {
7entry:
8; CHECK: multu
9; CHECK: mflo
10; CHECK: mfhi
11  %asmtmp = tail call %struct.DWstruct asm "multu $2,$3", "={lo},={hi},d,d"( i32 %u, i32 %v ) nounwind
12  %asmresult = extractvalue %struct.DWstruct %asmtmp, 0
13  %asmresult1 = extractvalue %struct.DWstruct %asmtmp, 1    ; <i32> [#uses=1]
14  %res = add i32 %asmresult, %asmresult1
15  ret i32 %res
16}
17
18@gi2 = external global i32
19@gi1 = external global i32
20@gi0 = external global i32
21@gf0 = external global float
22@gf1 = external global float
23@gd0 = external global double
24@gd1 = external global double
25
26define void @foo0() nounwind {
27entry:
28; CHECK: addu
29  %0 = load i32* @gi1, align 4
30  %1 = load i32* @gi0, align 4
31  %2 = tail call i32 asm "addu $0, $1, $2", "=r,r,r"(i32 %0, i32 %1) nounwind
32  store i32 %2, i32* @gi2, align 4
33  ret void
34}
35
36define void @foo2() nounwind {
37entry:
38; CHECK: neg.s
39  %0 = load float* @gf1, align 4
40  %1 = tail call float asm "neg.s $0, $1", "=f,f"(float %0) nounwind
41  store float %1, float* @gf0, align 4
42  ret void
43}
44
45define void @foo3() nounwind {
46entry:
47; CHECK: neg.d
48  %0 = load double* @gd1, align 8
49  %1 = tail call double asm "neg.d $0, $1", "=f,f"(double %0) nounwind
50  store double %1, double* @gd0, align 8
51  ret void
52}
53
54; Check that RA doesn't allocate registers in the clobber list.
55; CHECK-LABEL: foo4:
56; CHECK: #APP
57; CHECK-NOT: ulh $2
58; CHECK: #NO_APP
59; CHECK: #APP
60; CHECK-NOT: $f0
61; CHECK: #NO_APP
62
63define void @foo4() {
64entry:
65  %0 = tail call i32 asm sideeffect "ulh $0,16($$sp)\0A\09", "=r,~{$2}"()
66  store i32 %0, i32* @gi2, align 4
67  %1 = load float* @gf0, align 4
68  %2 = tail call double asm sideeffect "cvt.d.s $0, $1\0A\09", "=f,f,~{$f0}"(float %1)
69  store double %2, double* @gd0, align 8
70  ret void
71}
72