1; RUN: llc -march=mipsel -mattr=+dsp < %s | FileCheck %s 2 3define i32 @test__builtin_mips_extr_w1(i32 %i0, i32, i64 %a0) nounwind { 4entry: 5; CHECK: extr.w 6 7 %1 = tail call i32 @llvm.mips.extr.w(i64 %a0, i32 15) 8 ret i32 %1 9} 10 11declare i32 @llvm.mips.extr.w(i64, i32) nounwind 12 13define i32 @test__builtin_mips_extr_w2(i32 %i0, i32, i64 %a0, i32 %a1) nounwind { 14entry: 15; CHECK: extrv.w 16 17 %1 = tail call i32 @llvm.mips.extr.w(i64 %a0, i32 %a1) 18 ret i32 %1 19} 20 21define i32 @test__builtin_mips_extr_r_w1(i32 %i0, i32, i64 %a0) nounwind { 22entry: 23; CHECK: extr_r.w 24 25 %1 = tail call i32 @llvm.mips.extr.r.w(i64 %a0, i32 15) 26 ret i32 %1 27} 28 29declare i32 @llvm.mips.extr.r.w(i64, i32) nounwind 30 31define i32 @test__builtin_mips_extr_s_h1(i32 %i0, i32, i64 %a0, i32 %a1) nounwind { 32entry: 33; CHECK: extrv_s.h 34 35 %1 = tail call i32 @llvm.mips.extr.s.h(i64 %a0, i32 %a1) 36 ret i32 %1 37} 38 39declare i32 @llvm.mips.extr.s.h(i64, i32) nounwind 40 41define i32 @test__builtin_mips_extr_rs_w1(i32 %i0, i32, i64 %a0) nounwind { 42entry: 43; CHECK: extr_rs.w 44 45 %1 = tail call i32 @llvm.mips.extr.rs.w(i64 %a0, i32 15) 46 ret i32 %1 47} 48 49declare i32 @llvm.mips.extr.rs.w(i64, i32) nounwind 50 51define i32 @test__builtin_mips_extr_rs_w2(i32 %i0, i32, i64 %a0, i32 %a1) nounwind { 52entry: 53; CHECK: extrv_rs.w 54 55 %1 = tail call i32 @llvm.mips.extr.rs.w(i64 %a0, i32 %a1) 56 ret i32 %1 57} 58 59define i32 @test__builtin_mips_extr_s_h2(i32 %i0, i32, i64 %a0) nounwind { 60entry: 61; CHECK: extr_s.h 62 63 %1 = tail call i32 @llvm.mips.extr.s.h(i64 %a0, i32 15) 64 ret i32 %1 65} 66 67define i32 @test__builtin_mips_extr_r_w2(i32 %i0, i32, i64 %a0, i32 %a1) nounwind { 68entry: 69; CHECK: extrv_r.w 70 71 %1 = tail call i32 @llvm.mips.extr.r.w(i64 %a0, i32 %a1) 72 ret i32 %1 73} 74 75define i32 @test__builtin_mips_extp1(i32 %i0, i32, i64 %a0) nounwind { 76entry: 77; CHECK: extp ${{[0-9]+}} 78 79 %1 = tail call i32 @llvm.mips.extp(i64 %a0, i32 15) 80 ret i32 %1 81} 82 83declare i32 @llvm.mips.extp(i64, i32) nounwind 84 85define i32 @test__builtin_mips_extp2(i32 %i0, i32, i64 %a0, i32 %a1) nounwind { 86entry: 87; CHECK: extpv 88 89 %1 = tail call i32 @llvm.mips.extp(i64 %a0, i32 %a1) 90 ret i32 %1 91} 92 93define i32 @test__builtin_mips_extpdp1(i32 %i0, i32, i64 %a0) nounwind { 94entry: 95; CHECK: extpdp ${{[0-9]+}} 96 97 %1 = tail call i32 @llvm.mips.extpdp(i64 %a0, i32 15) 98 ret i32 %1 99} 100 101declare i32 @llvm.mips.extpdp(i64, i32) nounwind 102 103define i32 @test__builtin_mips_extpdp2(i32 %i0, i32, i64 %a0, i32 %a1) nounwind { 104entry: 105; CHECK: extpdpv 106 107 %1 = tail call i32 @llvm.mips.extpdp(i64 %a0, i32 %a1) 108 ret i32 %1 109} 110 111define i64 @test__builtin_mips_dpau_h_qbl1(i32 %i0, i32, i64 %a0, i32 %a1.coerce, i32 %a2.coerce) nounwind readnone { 112entry: 113; CHECK: dpau.h.qbl 114 115 %1 = bitcast i32 %a1.coerce to <4 x i8> 116 %2 = bitcast i32 %a2.coerce to <4 x i8> 117 %3 = tail call i64 @llvm.mips.dpau.h.qbl(i64 %a0, <4 x i8> %1, <4 x i8> %2) 118 ret i64 %3 119} 120 121declare i64 @llvm.mips.dpau.h.qbl(i64, <4 x i8>, <4 x i8>) nounwind readnone 122 123define i64 @test__builtin_mips_dpau_h_qbr1(i32 %i0, i32, i64 %a0, i32 %a1.coerce, i32 %a2.coerce) nounwind readnone { 124entry: 125; CHECK: dpau.h.qbr 126 127 %1 = bitcast i32 %a1.coerce to <4 x i8> 128 %2 = bitcast i32 %a2.coerce to <4 x i8> 129 %3 = tail call i64 @llvm.mips.dpau.h.qbr(i64 %a0, <4 x i8> %1, <4 x i8> %2) 130 ret i64 %3 131} 132 133declare i64 @llvm.mips.dpau.h.qbr(i64, <4 x i8>, <4 x i8>) nounwind readnone 134 135define i64 @test__builtin_mips_dpsu_h_qbl1(i32 %i0, i32, i64 %a0, i32 %a1.coerce, i32 %a2.coerce) nounwind readnone { 136entry: 137; CHECK: dpsu.h.qbl 138 139 %1 = bitcast i32 %a1.coerce to <4 x i8> 140 %2 = bitcast i32 %a2.coerce to <4 x i8> 141 %3 = tail call i64 @llvm.mips.dpsu.h.qbl(i64 %a0, <4 x i8> %1, <4 x i8> %2) 142 ret i64 %3 143} 144 145declare i64 @llvm.mips.dpsu.h.qbl(i64, <4 x i8>, <4 x i8>) nounwind readnone 146 147define i64 @test__builtin_mips_dpsu_h_qbr1(i32 %i0, i32, i64 %a0, i32 %a1.coerce, i32 %a2.coerce) nounwind readnone { 148entry: 149; CHECK: dpsu.h.qbr 150 151 %1 = bitcast i32 %a1.coerce to <4 x i8> 152 %2 = bitcast i32 %a2.coerce to <4 x i8> 153 %3 = tail call i64 @llvm.mips.dpsu.h.qbr(i64 %a0, <4 x i8> %1, <4 x i8> %2) 154 ret i64 %3 155} 156 157declare i64 @llvm.mips.dpsu.h.qbr(i64, <4 x i8>, <4 x i8>) nounwind readnone 158 159define i64 @test__builtin_mips_dpaq_s_w_ph1(i32 %i0, i32, i64 %a0, i32 %a1.coerce, i32 %a2.coerce) nounwind { 160entry: 161; CHECK: dpaq_s.w.ph 162 163 %1 = bitcast i32 %a1.coerce to <2 x i16> 164 %2 = bitcast i32 %a2.coerce to <2 x i16> 165 %3 = tail call i64 @llvm.mips.dpaq.s.w.ph(i64 %a0, <2 x i16> %1, <2 x i16> %2) 166 ret i64 %3 167} 168 169declare i64 @llvm.mips.dpaq.s.w.ph(i64, <2 x i16>, <2 x i16>) nounwind 170 171define i64 @test__builtin_mips_dpaq_sa_l_w1(i32 %i0, i32, i64 %a0, i32 %a1, i32 %a2) nounwind { 172entry: 173; CHECK: dpaq_sa.l.w 174 175 %1 = tail call i64 @llvm.mips.dpaq.sa.l.w(i64 %a0, i32 %a1, i32 %a2) 176 ret i64 %1 177} 178 179declare i64 @llvm.mips.dpaq.sa.l.w(i64, i32, i32) nounwind 180 181define i64 @test__builtin_mips_dpsq_s_w_ph1(i32 %i0, i32, i64 %a0, i32 %a1.coerce, i32 %a2.coerce) nounwind { 182entry: 183; CHECK: dpsq_s.w.ph 184 185 %1 = bitcast i32 %a1.coerce to <2 x i16> 186 %2 = bitcast i32 %a2.coerce to <2 x i16> 187 %3 = tail call i64 @llvm.mips.dpsq.s.w.ph(i64 %a0, <2 x i16> %1, <2 x i16> %2) 188 ret i64 %3 189} 190 191declare i64 @llvm.mips.dpsq.s.w.ph(i64, <2 x i16>, <2 x i16>) nounwind 192 193define i64 @test__builtin_mips_dpsq_sa_l_w1(i32 %i0, i32, i64 %a0, i32 %a1, i32 %a2) nounwind { 194entry: 195; CHECK: dpsq_sa.l.w 196 197 %1 = tail call i64 @llvm.mips.dpsq.sa.l.w(i64 %a0, i32 %a1, i32 %a2) 198 ret i64 %1 199} 200 201declare i64 @llvm.mips.dpsq.sa.l.w(i64, i32, i32) nounwind 202 203define i64 @test__builtin_mips_mulsaq_s_w_ph1(i32 %i0, i32, i64 %a0, i32 %a1.coerce, i32 %a2.coerce) nounwind { 204entry: 205; CHECK: mulsaq_s.w.ph 206 207 %1 = bitcast i32 %a1.coerce to <2 x i16> 208 %2 = bitcast i32 %a2.coerce to <2 x i16> 209 %3 = tail call i64 @llvm.mips.mulsaq.s.w.ph(i64 %a0, <2 x i16> %1, <2 x i16> %2) 210 ret i64 %3 211} 212 213declare i64 @llvm.mips.mulsaq.s.w.ph(i64, <2 x i16>, <2 x i16>) nounwind 214 215define i64 @test__builtin_mips_maq_s_w_phl1(i32 %i0, i32, i64 %a0, i32 %a1.coerce, i32 %a2.coerce) nounwind { 216entry: 217; CHECK: maq_s.w.phl 218 219 %1 = bitcast i32 %a1.coerce to <2 x i16> 220 %2 = bitcast i32 %a2.coerce to <2 x i16> 221 %3 = tail call i64 @llvm.mips.maq.s.w.phl(i64 %a0, <2 x i16> %1, <2 x i16> %2) 222 ret i64 %3 223} 224 225declare i64 @llvm.mips.maq.s.w.phl(i64, <2 x i16>, <2 x i16>) nounwind 226 227define i64 @test__builtin_mips_maq_s_w_phr1(i32 %i0, i32, i64 %a0, i32 %a1.coerce, i32 %a2.coerce) nounwind { 228entry: 229; CHECK: maq_s.w.phr 230 231 %1 = bitcast i32 %a1.coerce to <2 x i16> 232 %2 = bitcast i32 %a2.coerce to <2 x i16> 233 %3 = tail call i64 @llvm.mips.maq.s.w.phr(i64 %a0, <2 x i16> %1, <2 x i16> %2) 234 ret i64 %3 235} 236 237declare i64 @llvm.mips.maq.s.w.phr(i64, <2 x i16>, <2 x i16>) nounwind 238 239define i64 @test__builtin_mips_maq_sa_w_phl1(i32 %i0, i32, i64 %a0, i32 %a1.coerce, i32 %a2.coerce) nounwind { 240entry: 241; CHECK: maq_sa.w.phl 242 243 %1 = bitcast i32 %a1.coerce to <2 x i16> 244 %2 = bitcast i32 %a2.coerce to <2 x i16> 245 %3 = tail call i64 @llvm.mips.maq.sa.w.phl(i64 %a0, <2 x i16> %1, <2 x i16> %2) 246 ret i64 %3 247} 248 249declare i64 @llvm.mips.maq.sa.w.phl(i64, <2 x i16>, <2 x i16>) nounwind 250 251define i64 @test__builtin_mips_maq_sa_w_phr1(i32 %i0, i32, i64 %a0, i32 %a1.coerce, i32 %a2.coerce) nounwind { 252entry: 253; CHECK: maq_sa.w.phr 254 255 %1 = bitcast i32 %a1.coerce to <2 x i16> 256 %2 = bitcast i32 %a2.coerce to <2 x i16> 257 %3 = tail call i64 @llvm.mips.maq.sa.w.phr(i64 %a0, <2 x i16> %1, <2 x i16> %2) 258 ret i64 %3 259} 260 261declare i64 @llvm.mips.maq.sa.w.phr(i64, <2 x i16>, <2 x i16>) nounwind 262 263define i64 @test__builtin_mips_shilo1(i32 %i0, i32, i64 %a0) nounwind readnone { 264entry: 265; CHECK: shilo $ac{{[0-9]}} 266 267 %1 = tail call i64 @llvm.mips.shilo(i64 %a0, i32 0) 268 ret i64 %1 269} 270 271declare i64 @llvm.mips.shilo(i64, i32) nounwind readnone 272 273define i64 @test__builtin_mips_shilo2(i32 %i0, i32, i64 %a0, i32 %a1) nounwind readnone { 274entry: 275; CHECK: shilov 276 277 %1 = tail call i64 @llvm.mips.shilo(i64 %a0, i32 %a1) 278 ret i64 %1 279} 280 281define i64 @test__builtin_mips_mthlip1(i32 %i0, i32, i64 %a0, i32 %a1) nounwind { 282entry: 283; CHECK: mthlip ${{[0-9]+}} 284 285 %1 = tail call i64 @llvm.mips.mthlip(i64 %a0, i32 %a1) 286 ret i64 %1 287} 288 289declare i64 @llvm.mips.mthlip(i64, i32) nounwind 290 291define i32 @test__builtin_mips_bposge321(i32 %i0) nounwind readonly { 292entry: 293; CHECK: bposge32 $BB{{[0-9]+}} 294 295 %0 = tail call i32 @llvm.mips.bposge32() 296 ret i32 %0 297} 298 299declare i32 @llvm.mips.bposge32() nounwind readonly 300 301define i64 @test__builtin_mips_madd1(i32 %i0, i32, i64 %a0, i32 %a1, i32 %a2) nounwind readnone { 302entry: 303; CHECK: madd $ac{{[0-9]}} 304 305 %1 = tail call i64 @llvm.mips.madd(i64 %a0, i32 %a1, i32 %a2) 306 ret i64 %1 307} 308 309declare i64 @llvm.mips.madd(i64, i32, i32) nounwind readnone 310 311define i64 @test__builtin_mips_maddu1(i32 %i0, i32, i64 %a0, i32 %a1, i32 %a2) nounwind readnone { 312entry: 313; CHECK: maddu $ac{{[0-9]}} 314 315 %1 = tail call i64 @llvm.mips.maddu(i64 %a0, i32 %a1, i32 %a2) 316 ret i64 %1 317} 318 319declare i64 @llvm.mips.maddu(i64, i32, i32) nounwind readnone 320 321define i64 @test__builtin_mips_msub1(i32 %i0, i32, i64 %a0, i32 %a1, i32 %a2) nounwind readnone { 322entry: 323; CHECK: msub $ac{{[0-9]}} 324 325 %1 = tail call i64 @llvm.mips.msub(i64 %a0, i32 %a1, i32 %a2) 326 ret i64 %1 327} 328 329declare i64 @llvm.mips.msub(i64, i32, i32) nounwind readnone 330 331define i64 @test__builtin_mips_msubu1(i32 %i0, i32, i64 %a0, i32 %a1, i32 %a2) nounwind readnone { 332entry: 333; CHECK: msubu $ac{{[0-9]}} 334 335 %1 = tail call i64 @llvm.mips.msubu(i64 %a0, i32 %a1, i32 %a2) 336 ret i64 %1 337} 338 339declare i64 @llvm.mips.msubu(i64, i32, i32) nounwind readnone 340 341define i64 @test__builtin_mips_mult1(i32 %i0, i32 %a0, i32 %a1) nounwind readnone { 342entry: 343; CHECK: mult $ac{{[0-9]}} 344 345 %0 = tail call i64 @llvm.mips.mult(i32 %a0, i32 %a1) 346 ret i64 %0 347} 348 349declare i64 @llvm.mips.mult(i32, i32) nounwind readnone 350 351define i64 @test__builtin_mips_multu1(i32 %i0, i32 %a0, i32 %a1) nounwind readnone { 352entry: 353; CHECK: multu $ac{{[0-9]}} 354 355 %0 = tail call i64 @llvm.mips.multu(i32 %a0, i32 %a1) 356 ret i64 %0 357} 358 359declare i64 @llvm.mips.multu(i32, i32) nounwind readnone 360 361define { i32 } @test__builtin_mips_addq_ph1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind { 362entry: 363; CHECK: addq.ph 364 365 %0 = bitcast i32 %a0.coerce to <2 x i16> 366 %1 = bitcast i32 %a1.coerce to <2 x i16> 367 %2 = tail call <2 x i16> @llvm.mips.addq.ph(<2 x i16> %0, <2 x i16> %1) 368 %3 = bitcast <2 x i16> %2 to i32 369 %.fca.0.insert = insertvalue { i32 } undef, i32 %3, 0 370 ret { i32 } %.fca.0.insert 371} 372 373declare <2 x i16> @llvm.mips.addq.ph(<2 x i16>, <2 x i16>) nounwind 374 375define { i32 } @test__builtin_mips_addq_s_ph1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind { 376entry: 377; CHECK: addq_s.ph 378 379 %0 = bitcast i32 %a0.coerce to <2 x i16> 380 %1 = bitcast i32 %a1.coerce to <2 x i16> 381 %2 = tail call <2 x i16> @llvm.mips.addq.s.ph(<2 x i16> %0, <2 x i16> %1) 382 %3 = bitcast <2 x i16> %2 to i32 383 %.fca.0.insert = insertvalue { i32 } undef, i32 %3, 0 384 ret { i32 } %.fca.0.insert 385} 386 387declare <2 x i16> @llvm.mips.addq.s.ph(<2 x i16>, <2 x i16>) nounwind 388 389define i32 @test__builtin_mips_addq_s_w1(i32 %i0, i32 %a0, i32 %a1) nounwind { 390entry: 391; CHECK: addq_s.w 392 393 %0 = tail call i32 @llvm.mips.addq.s.w(i32 %a0, i32 %a1) 394 ret i32 %0 395} 396 397declare i32 @llvm.mips.addq.s.w(i32, i32) nounwind 398 399define { i32 } @test__builtin_mips_addu_qb1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind { 400entry: 401; CHECK: addu.qb 402 403 %0 = bitcast i32 %a0.coerce to <4 x i8> 404 %1 = bitcast i32 %a1.coerce to <4 x i8> 405 %2 = tail call <4 x i8> @llvm.mips.addu.qb(<4 x i8> %0, <4 x i8> %1) 406 %3 = bitcast <4 x i8> %2 to i32 407 %.fca.0.insert = insertvalue { i32 } undef, i32 %3, 0 408 ret { i32 } %.fca.0.insert 409} 410 411declare <4 x i8> @llvm.mips.addu.qb(<4 x i8>, <4 x i8>) nounwind 412 413define { i32 } @test__builtin_mips_addu_s_qb1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind { 414entry: 415; CHECK: addu_s.qb 416 417 %0 = bitcast i32 %a0.coerce to <4 x i8> 418 %1 = bitcast i32 %a1.coerce to <4 x i8> 419 %2 = tail call <4 x i8> @llvm.mips.addu.s.qb(<4 x i8> %0, <4 x i8> %1) 420 %3 = bitcast <4 x i8> %2 to i32 421 %.fca.0.insert = insertvalue { i32 } undef, i32 %3, 0 422 ret { i32 } %.fca.0.insert 423} 424 425declare <4 x i8> @llvm.mips.addu.s.qb(<4 x i8>, <4 x i8>) nounwind 426 427define { i32 } @test__builtin_mips_subq_ph1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind { 428entry: 429; CHECK: subq.ph 430 431 %0 = bitcast i32 %a0.coerce to <2 x i16> 432 %1 = bitcast i32 %a1.coerce to <2 x i16> 433 %2 = tail call <2 x i16> @llvm.mips.subq.ph(<2 x i16> %0, <2 x i16> %1) 434 %3 = bitcast <2 x i16> %2 to i32 435 %.fca.0.insert = insertvalue { i32 } undef, i32 %3, 0 436 ret { i32 } %.fca.0.insert 437} 438 439declare <2 x i16> @llvm.mips.subq.ph(<2 x i16>, <2 x i16>) nounwind 440 441define { i32 } @test__builtin_mips_subq_s_ph1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind { 442entry: 443; CHECK: subq_s.ph 444 445 %0 = bitcast i32 %a0.coerce to <2 x i16> 446 %1 = bitcast i32 %a1.coerce to <2 x i16> 447 %2 = tail call <2 x i16> @llvm.mips.subq.s.ph(<2 x i16> %0, <2 x i16> %1) 448 %3 = bitcast <2 x i16> %2 to i32 449 %.fca.0.insert = insertvalue { i32 } undef, i32 %3, 0 450 ret { i32 } %.fca.0.insert 451} 452 453declare <2 x i16> @llvm.mips.subq.s.ph(<2 x i16>, <2 x i16>) nounwind 454 455define i32 @test__builtin_mips_subq_s_w1(i32 %i0, i32 %a0, i32 %a1) nounwind { 456entry: 457; CHECK: subq_s.w 458 459 %0 = tail call i32 @llvm.mips.subq.s.w(i32 %a0, i32 %a1) 460 ret i32 %0 461} 462 463declare i32 @llvm.mips.subq.s.w(i32, i32) nounwind 464 465define { i32 } @test__builtin_mips_subu_qb1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind { 466entry: 467; CHECK: subu.qb 468 469 %0 = bitcast i32 %a0.coerce to <4 x i8> 470 %1 = bitcast i32 %a1.coerce to <4 x i8> 471 %2 = tail call <4 x i8> @llvm.mips.subu.qb(<4 x i8> %0, <4 x i8> %1) 472 %3 = bitcast <4 x i8> %2 to i32 473 %.fca.0.insert = insertvalue { i32 } undef, i32 %3, 0 474 ret { i32 } %.fca.0.insert 475} 476 477declare <4 x i8> @llvm.mips.subu.qb(<4 x i8>, <4 x i8>) nounwind 478 479define { i32 } @test__builtin_mips_subu_s_qb1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind { 480entry: 481; CHECK: subu_s.qb 482 483 %0 = bitcast i32 %a0.coerce to <4 x i8> 484 %1 = bitcast i32 %a1.coerce to <4 x i8> 485 %2 = tail call <4 x i8> @llvm.mips.subu.s.qb(<4 x i8> %0, <4 x i8> %1) 486 %3 = bitcast <4 x i8> %2 to i32 487 %.fca.0.insert = insertvalue { i32 } undef, i32 %3, 0 488 ret { i32 } %.fca.0.insert 489} 490 491declare <4 x i8> @llvm.mips.subu.s.qb(<4 x i8>, <4 x i8>) nounwind 492 493define i32 @test__builtin_mips_addsc1(i32 %i0, i32 %a0, i32 %a1) nounwind { 494entry: 495; CHECK: addsc ${{[0-9]+}} 496 497 %0 = tail call i32 @llvm.mips.addsc(i32 %a0, i32 %a1) 498 ret i32 %0 499} 500 501declare i32 @llvm.mips.addsc(i32, i32) nounwind 502 503define i32 @test__builtin_mips_addwc1(i32 %i0, i32 %a0, i32 %a1) nounwind { 504entry: 505; CHECK: addwc ${{[0-9]+}} 506 507 %0 = tail call i32 @llvm.mips.addwc(i32 %a0, i32 %a1) 508 ret i32 %0 509} 510 511declare i32 @llvm.mips.addwc(i32, i32) nounwind 512 513define i32 @test__builtin_mips_modsub1(i32 %i0, i32 %a0, i32 %a1) nounwind readnone { 514entry: 515; CHECK: modsub ${{[0-9]+}} 516 517 %0 = tail call i32 @llvm.mips.modsub(i32 %a0, i32 %a1) 518 ret i32 %0 519} 520 521declare i32 @llvm.mips.modsub(i32, i32) nounwind readnone 522 523define i32 @test__builtin_mips_raddu_w_qb1(i32 %i0, i32 %a0.coerce) nounwind readnone { 524entry: 525; CHECK: raddu.w.qb 526 527 %0 = bitcast i32 %a0.coerce to <4 x i8> 528 %1 = tail call i32 @llvm.mips.raddu.w.qb(<4 x i8> %0) 529 ret i32 %1 530} 531 532declare i32 @llvm.mips.raddu.w.qb(<4 x i8>) nounwind readnone 533 534define { i32 } @test__builtin_mips_muleu_s_ph_qbl1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind { 535entry: 536; CHECK: muleu_s.ph.qbl 537 538 %0 = bitcast i32 %a0.coerce to <4 x i8> 539 %1 = bitcast i32 %a1.coerce to <2 x i16> 540 %2 = tail call <2 x i16> @llvm.mips.muleu.s.ph.qbl(<4 x i8> %0, <2 x i16> %1) 541 %3 = bitcast <2 x i16> %2 to i32 542 %.fca.0.insert = insertvalue { i32 } undef, i32 %3, 0 543 ret { i32 } %.fca.0.insert 544} 545 546declare <2 x i16> @llvm.mips.muleu.s.ph.qbl(<4 x i8>, <2 x i16>) nounwind 547 548define { i32 } @test__builtin_mips_muleu_s_ph_qbr1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind { 549entry: 550; CHECK: muleu_s.ph.qbr 551 552 %0 = bitcast i32 %a0.coerce to <4 x i8> 553 %1 = bitcast i32 %a1.coerce to <2 x i16> 554 %2 = tail call <2 x i16> @llvm.mips.muleu.s.ph.qbr(<4 x i8> %0, <2 x i16> %1) 555 %3 = bitcast <2 x i16> %2 to i32 556 %.fca.0.insert = insertvalue { i32 } undef, i32 %3, 0 557 ret { i32 } %.fca.0.insert 558} 559 560declare <2 x i16> @llvm.mips.muleu.s.ph.qbr(<4 x i8>, <2 x i16>) nounwind 561 562define { i32 } @test__builtin_mips_mulq_rs_ph1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind { 563entry: 564; CHECK: mulq_rs.ph 565 566 %0 = bitcast i32 %a0.coerce to <2 x i16> 567 %1 = bitcast i32 %a1.coerce to <2 x i16> 568 %2 = tail call <2 x i16> @llvm.mips.mulq.rs.ph(<2 x i16> %0, <2 x i16> %1) 569 %3 = bitcast <2 x i16> %2 to i32 570 %.fca.0.insert = insertvalue { i32 } undef, i32 %3, 0 571 ret { i32 } %.fca.0.insert 572} 573 574declare <2 x i16> @llvm.mips.mulq.rs.ph(<2 x i16>, <2 x i16>) nounwind 575 576define i32 @test__builtin_mips_muleq_s_w_phl1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind { 577entry: 578; CHECK: muleq_s.w.phl 579 580 %0 = bitcast i32 %a0.coerce to <2 x i16> 581 %1 = bitcast i32 %a1.coerce to <2 x i16> 582 %2 = tail call i32 @llvm.mips.muleq.s.w.phl(<2 x i16> %0, <2 x i16> %1) 583 ret i32 %2 584} 585 586declare i32 @llvm.mips.muleq.s.w.phl(<2 x i16>, <2 x i16>) nounwind 587 588define i32 @test__builtin_mips_muleq_s_w_phr1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind { 589entry: 590; CHECK: muleq_s.w.phr 591 592 %0 = bitcast i32 %a0.coerce to <2 x i16> 593 %1 = bitcast i32 %a1.coerce to <2 x i16> 594 %2 = tail call i32 @llvm.mips.muleq.s.w.phr(<2 x i16> %0, <2 x i16> %1) 595 ret i32 %2 596} 597 598declare i32 @llvm.mips.muleq.s.w.phr(<2 x i16>, <2 x i16>) nounwind 599 600define { i32 } @test__builtin_mips_precrq_qb_ph1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind readnone { 601entry: 602; CHECK: precrq.qb.ph 603 604 %0 = bitcast i32 %a0.coerce to <2 x i16> 605 %1 = bitcast i32 %a1.coerce to <2 x i16> 606 %2 = tail call <4 x i8> @llvm.mips.precrq.qb.ph(<2 x i16> %0, <2 x i16> %1) 607 %3 = bitcast <4 x i8> %2 to i32 608 %.fca.0.insert = insertvalue { i32 } undef, i32 %3, 0 609 ret { i32 } %.fca.0.insert 610} 611 612declare <4 x i8> @llvm.mips.precrq.qb.ph(<2 x i16>, <2 x i16>) nounwind readnone 613 614define { i32 } @test__builtin_mips_precrq_ph_w1(i32 %i0, i32 %a0, i32 %a1) nounwind readnone { 615entry: 616; CHECK: precrq.ph.w 617 618 %0 = tail call <2 x i16> @llvm.mips.precrq.ph.w(i32 %a0, i32 %a1) 619 %1 = bitcast <2 x i16> %0 to i32 620 %.fca.0.insert = insertvalue { i32 } undef, i32 %1, 0 621 ret { i32 } %.fca.0.insert 622} 623 624declare <2 x i16> @llvm.mips.precrq.ph.w(i32, i32) nounwind readnone 625 626define { i32 } @test__builtin_mips_precrq_rs_ph_w1(i32 %i0, i32 %a0, i32 %a1) nounwind { 627entry: 628; CHECK: precrq_rs.ph.w 629 630 %0 = tail call <2 x i16> @llvm.mips.precrq.rs.ph.w(i32 %a0, i32 %a1) 631 %1 = bitcast <2 x i16> %0 to i32 632 %.fca.0.insert = insertvalue { i32 } undef, i32 %1, 0 633 ret { i32 } %.fca.0.insert 634} 635 636declare <2 x i16> @llvm.mips.precrq.rs.ph.w(i32, i32) nounwind 637 638define { i32 } @test__builtin_mips_precrqu_s_qb_ph1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind { 639entry: 640; CHECK: precrqu_s.qb.ph 641 642 %0 = bitcast i32 %a0.coerce to <2 x i16> 643 %1 = bitcast i32 %a1.coerce to <2 x i16> 644 %2 = tail call <4 x i8> @llvm.mips.precrqu.s.qb.ph(<2 x i16> %0, <2 x i16> %1) 645 %3 = bitcast <4 x i8> %2 to i32 646 %.fca.0.insert = insertvalue { i32 } undef, i32 %3, 0 647 ret { i32 } %.fca.0.insert 648} 649 650declare <4 x i8> @llvm.mips.precrqu.s.qb.ph(<2 x i16>, <2 x i16>) nounwind 651 652 653define i32 @test__builtin_mips_cmpu_eq_qb1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind { 654entry: 655; CHECK: cmpu.eq.qb 656 657 %0 = bitcast i32 %a0.coerce to <4 x i8> 658 %1 = bitcast i32 %a1.coerce to <4 x i8> 659 tail call void @llvm.mips.cmpu.eq.qb(<4 x i8> %0, <4 x i8> %1) 660 %2 = tail call i32 @llvm.mips.rddsp(i32 31) 661 ret i32 %2 662} 663 664declare void @llvm.mips.cmpu.eq.qb(<4 x i8>, <4 x i8>) nounwind 665 666declare i32 @llvm.mips.rddsp(i32) nounwind readonly 667 668define i32 @test__builtin_mips_cmpu_lt_qb1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind { 669entry: 670; CHECK: cmpu.lt.qb 671 672 %0 = bitcast i32 %a0.coerce to <4 x i8> 673 %1 = bitcast i32 %a1.coerce to <4 x i8> 674 tail call void @llvm.mips.cmpu.lt.qb(<4 x i8> %0, <4 x i8> %1) 675 %2 = tail call i32 @llvm.mips.rddsp(i32 31) 676 ret i32 %2 677} 678 679declare void @llvm.mips.cmpu.lt.qb(<4 x i8>, <4 x i8>) nounwind 680 681define i32 @test__builtin_mips_cmpu_le_qb1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind { 682entry: 683; CHECK: cmpu.le.qb 684 685 %0 = bitcast i32 %a0.coerce to <4 x i8> 686 %1 = bitcast i32 %a1.coerce to <4 x i8> 687 tail call void @llvm.mips.cmpu.le.qb(<4 x i8> %0, <4 x i8> %1) 688 %2 = tail call i32 @llvm.mips.rddsp(i32 31) 689 ret i32 %2 690} 691 692declare void @llvm.mips.cmpu.le.qb(<4 x i8>, <4 x i8>) nounwind 693 694define i32 @test__builtin_mips_cmpgu_eq_qb1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind { 695entry: 696; CHECK: cmpgu.eq.qb 697 698 %0 = bitcast i32 %a0.coerce to <4 x i8> 699 %1 = bitcast i32 %a1.coerce to <4 x i8> 700 %2 = tail call i32 @llvm.mips.cmpgu.eq.qb(<4 x i8> %0, <4 x i8> %1) 701 ret i32 %2 702} 703 704declare i32 @llvm.mips.cmpgu.eq.qb(<4 x i8>, <4 x i8>) nounwind 705 706define i32 @test__builtin_mips_cmpgu_lt_qb1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind { 707entry: 708; CHECK: cmpgu.lt.qb 709 710 %0 = bitcast i32 %a0.coerce to <4 x i8> 711 %1 = bitcast i32 %a1.coerce to <4 x i8> 712 %2 = tail call i32 @llvm.mips.cmpgu.lt.qb(<4 x i8> %0, <4 x i8> %1) 713 ret i32 %2 714} 715 716declare i32 @llvm.mips.cmpgu.lt.qb(<4 x i8>, <4 x i8>) nounwind 717 718define i32 @test__builtin_mips_cmpgu_le_qb1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind { 719entry: 720; CHECK: cmpgu.le.qb 721 722 %0 = bitcast i32 %a0.coerce to <4 x i8> 723 %1 = bitcast i32 %a1.coerce to <4 x i8> 724 %2 = tail call i32 @llvm.mips.cmpgu.le.qb(<4 x i8> %0, <4 x i8> %1) 725 ret i32 %2 726} 727 728declare i32 @llvm.mips.cmpgu.le.qb(<4 x i8>, <4 x i8>) nounwind 729 730define i32 @test__builtin_mips_cmp_eq_ph1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind { 731entry: 732; CHECK: cmp.eq.ph 733 734 %0 = bitcast i32 %a0.coerce to <2 x i16> 735 %1 = bitcast i32 %a1.coerce to <2 x i16> 736 tail call void @llvm.mips.cmp.eq.ph(<2 x i16> %0, <2 x i16> %1) 737 %2 = tail call i32 @llvm.mips.rddsp(i32 31) 738 ret i32 %2 739} 740 741declare void @llvm.mips.cmp.eq.ph(<2 x i16>, <2 x i16>) nounwind 742 743define i32 @test__builtin_mips_cmp_lt_ph1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind { 744entry: 745; CHECK: cmp.lt.ph 746 747 %0 = bitcast i32 %a0.coerce to <2 x i16> 748 %1 = bitcast i32 %a1.coerce to <2 x i16> 749 tail call void @llvm.mips.cmp.lt.ph(<2 x i16> %0, <2 x i16> %1) 750 %2 = tail call i32 @llvm.mips.rddsp(i32 31) 751 ret i32 %2 752} 753 754declare void @llvm.mips.cmp.lt.ph(<2 x i16>, <2 x i16>) nounwind 755 756define i32 @test__builtin_mips_cmp_le_ph1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind { 757entry: 758; CHECK: cmp.le.ph 759 760 %0 = bitcast i32 %a0.coerce to <2 x i16> 761 %1 = bitcast i32 %a1.coerce to <2 x i16> 762 tail call void @llvm.mips.cmp.le.ph(<2 x i16> %0, <2 x i16> %1) 763 %2 = tail call i32 @llvm.mips.rddsp(i32 31) 764 ret i32 %2 765} 766 767declare void @llvm.mips.cmp.le.ph(<2 x i16>, <2 x i16>) nounwind 768 769define { i32 } @test__builtin_mips_pick_qb1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind readonly { 770entry: 771; CHECK: pick.qb 772 773 %0 = bitcast i32 %a0.coerce to <4 x i8> 774 %1 = bitcast i32 %a1.coerce to <4 x i8> 775 tail call void @llvm.mips.wrdsp(i32 %i0, i32 16) 776 %2 = tail call <4 x i8> @llvm.mips.pick.qb(<4 x i8> %0, <4 x i8> %1) 777 %3 = bitcast <4 x i8> %2 to i32 778 %.fca.0.insert = insertvalue { i32 } undef, i32 %3, 0 779 ret { i32 } %.fca.0.insert 780} 781 782declare <4 x i8> @llvm.mips.pick.qb(<4 x i8>, <4 x i8>) nounwind readonly 783 784define { i32 } @test__builtin_mips_pick_ph1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind readonly { 785entry: 786; CHECK: pick.ph 787 788 %0 = bitcast i32 %a0.coerce to <2 x i16> 789 %1 = bitcast i32 %a1.coerce to <2 x i16> 790 tail call void @llvm.mips.wrdsp(i32 %i0, i32 16) 791 %2 = tail call <2 x i16> @llvm.mips.pick.ph(<2 x i16> %0, <2 x i16> %1) 792 %3 = bitcast <2 x i16> %2 to i32 793 %.fca.0.insert = insertvalue { i32 } undef, i32 %3, 0 794 ret { i32 } %.fca.0.insert 795} 796 797declare <2 x i16> @llvm.mips.pick.ph(<2 x i16>, <2 x i16>) nounwind readonly 798 799define { i32 } @test__builtin_mips_packrl_ph1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind readnone { 800entry: 801; CHECK: packrl.ph 802 803 %0 = bitcast i32 %a0.coerce to <2 x i16> 804 %1 = bitcast i32 %a1.coerce to <2 x i16> 805 %2 = tail call <2 x i16> @llvm.mips.packrl.ph(<2 x i16> %0, <2 x i16> %1) 806 %3 = bitcast <2 x i16> %2 to i32 807 %.fca.0.insert = insertvalue { i32 } undef, i32 %3, 0 808 ret { i32 } %.fca.0.insert 809} 810 811declare <2 x i16> @llvm.mips.packrl.ph(<2 x i16>, <2 x i16>) nounwind readnone 812 813define { i32 } @test__builtin_mips_shll_qb1(i32 %i0, i32 %a0.coerce) nounwind { 814entry: 815; CHECK: shll.qb 816 817 %0 = bitcast i32 %a0.coerce to <4 x i8> 818 %1 = tail call <4 x i8> @llvm.mips.shll.qb(<4 x i8> %0, i32 3) 819 %2 = bitcast <4 x i8> %1 to i32 820 %.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0 821 ret { i32 } %.fca.0.insert 822} 823 824declare <4 x i8> @llvm.mips.shll.qb(<4 x i8>, i32) nounwind 825 826define { i32 } @test__builtin_mips_shll_qb2(i32 %i0, i32 %a0.coerce, i32 %a1) nounwind { 827entry: 828; CHECK: shllv.qb 829 830 %0 = bitcast i32 %a0.coerce to <4 x i8> 831 %1 = tail call <4 x i8> @llvm.mips.shll.qb(<4 x i8> %0, i32 %a1) 832 %2 = bitcast <4 x i8> %1 to i32 833 %.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0 834 ret { i32 } %.fca.0.insert 835} 836 837define { i32 } @test__builtin_mips_shll_ph1(i32 %i0, i32 %a0.coerce) nounwind { 838entry: 839; CHECK: shll.ph 840 841 %0 = bitcast i32 %a0.coerce to <2 x i16> 842 %1 = tail call <2 x i16> @llvm.mips.shll.ph(<2 x i16> %0, i32 7) 843 %2 = bitcast <2 x i16> %1 to i32 844 %.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0 845 ret { i32 } %.fca.0.insert 846} 847 848declare <2 x i16> @llvm.mips.shll.ph(<2 x i16>, i32) nounwind 849 850define { i32 } @test__builtin_mips_shll_ph2(i32 %i0, i32 %a0.coerce, i32 %a1) nounwind { 851entry: 852; CHECK: shllv.ph 853 854 %0 = bitcast i32 %a0.coerce to <2 x i16> 855 %1 = tail call <2 x i16> @llvm.mips.shll.ph(<2 x i16> %0, i32 %a1) 856 %2 = bitcast <2 x i16> %1 to i32 857 %.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0 858 ret { i32 } %.fca.0.insert 859} 860 861define { i32 } @test__builtin_mips_shll_s_ph1(i32 %i0, i32 %a0.coerce) nounwind { 862entry: 863; CHECK: shll_s.ph 864 865 %0 = bitcast i32 %a0.coerce to <2 x i16> 866 %1 = tail call <2 x i16> @llvm.mips.shll.s.ph(<2 x i16> %0, i32 7) 867 %2 = bitcast <2 x i16> %1 to i32 868 %.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0 869 ret { i32 } %.fca.0.insert 870} 871 872declare <2 x i16> @llvm.mips.shll.s.ph(<2 x i16>, i32) nounwind 873 874define { i32 } @test__builtin_mips_shll_s_ph2(i32 %i0, i32 %a0.coerce, i32 %a1) nounwind { 875entry: 876; CHECK: shllv_s.ph 877 878 %0 = bitcast i32 %a0.coerce to <2 x i16> 879 %1 = tail call <2 x i16> @llvm.mips.shll.s.ph(<2 x i16> %0, i32 %a1) 880 %2 = bitcast <2 x i16> %1 to i32 881 %.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0 882 ret { i32 } %.fca.0.insert 883} 884 885define i32 @test__builtin_mips_shll_s_w1(i32 %i0, i32 %a0) nounwind { 886entry: 887; CHECK: shll_s.w 888 889 %0 = tail call i32 @llvm.mips.shll.s.w(i32 %a0, i32 15) 890 ret i32 %0 891} 892 893declare i32 @llvm.mips.shll.s.w(i32, i32) nounwind 894 895define i32 @test__builtin_mips_shll_s_w2(i32 %i0, i32 %a0, i32 %a1) nounwind { 896entry: 897; CHECK: shllv_s.w 898 899 %0 = tail call i32 @llvm.mips.shll.s.w(i32 %a0, i32 %a1) 900 ret i32 %0 901} 902 903define { i32 } @test__builtin_mips_shrl_qb1(i32 %i0, i32 %a0.coerce) nounwind readnone { 904entry: 905; CHECK: shrl.qb 906 907 %0 = bitcast i32 %a0.coerce to <4 x i8> 908 %1 = tail call <4 x i8> @llvm.mips.shrl.qb(<4 x i8> %0, i32 3) 909 %2 = bitcast <4 x i8> %1 to i32 910 %.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0 911 ret { i32 } %.fca.0.insert 912} 913 914declare <4 x i8> @llvm.mips.shrl.qb(<4 x i8>, i32) nounwind readnone 915 916define { i32 } @test__builtin_mips_shrl_qb2(i32 %i0, i32 %a0.coerce, i32 %a1) nounwind readnone { 917entry: 918; CHECK: shrlv.qb 919 920 %0 = bitcast i32 %a0.coerce to <4 x i8> 921 %1 = tail call <4 x i8> @llvm.mips.shrl.qb(<4 x i8> %0, i32 %a1) 922 %2 = bitcast <4 x i8> %1 to i32 923 %.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0 924 ret { i32 } %.fca.0.insert 925} 926 927define { i32 } @test__builtin_mips_shra_ph1(i32 %i0, i32 %a0.coerce) nounwind readnone { 928entry: 929; CHECK: shra.ph 930 931 %0 = bitcast i32 %a0.coerce to <2 x i16> 932 %1 = tail call <2 x i16> @llvm.mips.shra.ph(<2 x i16> %0, i32 7) 933 %2 = bitcast <2 x i16> %1 to i32 934 %.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0 935 ret { i32 } %.fca.0.insert 936} 937 938declare <2 x i16> @llvm.mips.shra.ph(<2 x i16>, i32) nounwind readnone 939 940define { i32 } @test__builtin_mips_shra_ph2(i32 %i0, i32 %a0.coerce, i32 %a1) nounwind readnone { 941entry: 942; CHECK: shrav.ph 943 944 %0 = bitcast i32 %a0.coerce to <2 x i16> 945 %1 = tail call <2 x i16> @llvm.mips.shra.ph(<2 x i16> %0, i32 %a1) 946 %2 = bitcast <2 x i16> %1 to i32 947 %.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0 948 ret { i32 } %.fca.0.insert 949} 950 951define { i32 } @test__builtin_mips_shra_r_ph1(i32 %i0, i32 %a0.coerce) nounwind readnone { 952entry: 953; CHECK: shra_r.ph 954 955 %0 = bitcast i32 %a0.coerce to <2 x i16> 956 %1 = tail call <2 x i16> @llvm.mips.shra.r.ph(<2 x i16> %0, i32 7) 957 %2 = bitcast <2 x i16> %1 to i32 958 %.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0 959 ret { i32 } %.fca.0.insert 960} 961 962declare <2 x i16> @llvm.mips.shra.r.ph(<2 x i16>, i32) nounwind readnone 963 964define { i32 } @test__builtin_mips_shra_r_ph2(i32 %i0, i32 %a0.coerce, i32 %a1) nounwind readnone { 965entry: 966; CHECK: shrav_r.ph 967 968 %0 = bitcast i32 %a0.coerce to <2 x i16> 969 %1 = tail call <2 x i16> @llvm.mips.shra.r.ph(<2 x i16> %0, i32 %a1) 970 %2 = bitcast <2 x i16> %1 to i32 971 %.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0 972 ret { i32 } %.fca.0.insert 973} 974 975define i32 @test__builtin_mips_shra_r_w1(i32 %i0, i32 %a0) nounwind readnone { 976entry: 977; CHECK: shra_r.w 978 979 %0 = tail call i32 @llvm.mips.shra.r.w(i32 %a0, i32 15) 980 ret i32 %0 981} 982 983declare i32 @llvm.mips.shra.r.w(i32, i32) nounwind readnone 984 985define i32 @test__builtin_mips_shra_r_w2(i32 %i0, i32 %a0, i32 %a1) nounwind readnone { 986entry: 987; CHECK: shrav_r.w 988 989 %0 = tail call i32 @llvm.mips.shra.r.w(i32 %a0, i32 %a1) 990 ret i32 %0 991} 992 993define { i32 } @test__builtin_mips_absq_s_ph1(i32 %i0, i32 %a0.coerce) nounwind { 994entry: 995; CHECK: absq_s.ph 996 997 %0 = bitcast i32 %a0.coerce to <2 x i16> 998 %1 = tail call <2 x i16> @llvm.mips.absq.s.ph(<2 x i16> %0) 999 %2 = bitcast <2 x i16> %1 to i32 1000 %.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0 1001 ret { i32 } %.fca.0.insert 1002} 1003 1004declare <2 x i16> @llvm.mips.absq.s.ph(<2 x i16>) nounwind 1005 1006define i32 @test__builtin_mips_absq_s_w1(i32 %i0, i32 %a0) nounwind { 1007entry: 1008; CHECK: absq_s.w 1009 1010 %0 = tail call i32 @llvm.mips.absq.s.w(i32 %a0) 1011 ret i32 %0 1012} 1013 1014declare i32 @llvm.mips.absq.s.w(i32) nounwind 1015 1016define i32 @test__builtin_mips_preceq_w_phl1(i32 %i0, i32 %a0.coerce) nounwind readnone { 1017entry: 1018; CHECK: preceq.w.phl 1019 1020 %0 = bitcast i32 %a0.coerce to <2 x i16> 1021 %1 = tail call i32 @llvm.mips.preceq.w.phl(<2 x i16> %0) 1022 ret i32 %1 1023} 1024 1025declare i32 @llvm.mips.preceq.w.phl(<2 x i16>) nounwind readnone 1026 1027define i32 @test__builtin_mips_preceq_w_phr1(i32 %i0, i32 %a0.coerce) nounwind readnone { 1028entry: 1029; CHECK: preceq.w.phr 1030 1031 %0 = bitcast i32 %a0.coerce to <2 x i16> 1032 %1 = tail call i32 @llvm.mips.preceq.w.phr(<2 x i16> %0) 1033 ret i32 %1 1034} 1035 1036declare i32 @llvm.mips.preceq.w.phr(<2 x i16>) nounwind readnone 1037 1038define { i32 } @test__builtin_mips_precequ_ph_qbl1(i32 %i0, i32 %a0.coerce) nounwind readnone { 1039entry: 1040; CHECK: precequ.ph.qbl 1041 1042 %0 = bitcast i32 %a0.coerce to <4 x i8> 1043 %1 = tail call <2 x i16> @llvm.mips.precequ.ph.qbl(<4 x i8> %0) 1044 %2 = bitcast <2 x i16> %1 to i32 1045 %.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0 1046 ret { i32 } %.fca.0.insert 1047} 1048 1049declare <2 x i16> @llvm.mips.precequ.ph.qbl(<4 x i8>) nounwind readnone 1050 1051define { i32 } @test__builtin_mips_precequ_ph_qbr1(i32 %i0, i32 %a0.coerce) nounwind readnone { 1052entry: 1053; CHECK: precequ.ph.qbr 1054 1055 %0 = bitcast i32 %a0.coerce to <4 x i8> 1056 %1 = tail call <2 x i16> @llvm.mips.precequ.ph.qbr(<4 x i8> %0) 1057 %2 = bitcast <2 x i16> %1 to i32 1058 %.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0 1059 ret { i32 } %.fca.0.insert 1060} 1061 1062declare <2 x i16> @llvm.mips.precequ.ph.qbr(<4 x i8>) nounwind readnone 1063 1064define { i32 } @test__builtin_mips_precequ_ph_qbla1(i32 %i0, i32 %a0.coerce) nounwind readnone { 1065entry: 1066; CHECK: precequ.ph.qbla 1067 1068 %0 = bitcast i32 %a0.coerce to <4 x i8> 1069 %1 = tail call <2 x i16> @llvm.mips.precequ.ph.qbla(<4 x i8> %0) 1070 %2 = bitcast <2 x i16> %1 to i32 1071 %.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0 1072 ret { i32 } %.fca.0.insert 1073} 1074 1075declare <2 x i16> @llvm.mips.precequ.ph.qbla(<4 x i8>) nounwind readnone 1076 1077define { i32 } @test__builtin_mips_precequ_ph_qbra1(i32 %i0, i32 %a0.coerce) nounwind readnone { 1078entry: 1079; CHECK: precequ.ph.qbra 1080 1081 %0 = bitcast i32 %a0.coerce to <4 x i8> 1082 %1 = tail call <2 x i16> @llvm.mips.precequ.ph.qbra(<4 x i8> %0) 1083 %2 = bitcast <2 x i16> %1 to i32 1084 %.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0 1085 ret { i32 } %.fca.0.insert 1086} 1087 1088declare <2 x i16> @llvm.mips.precequ.ph.qbra(<4 x i8>) nounwind readnone 1089 1090define { i32 } @test__builtin_mips_preceu_ph_qbl1(i32 %i0, i32 %a0.coerce) nounwind readnone { 1091entry: 1092; CHECK: preceu.ph.qbl 1093 1094 %0 = bitcast i32 %a0.coerce to <4 x i8> 1095 %1 = tail call <2 x i16> @llvm.mips.preceu.ph.qbl(<4 x i8> %0) 1096 %2 = bitcast <2 x i16> %1 to i32 1097 %.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0 1098 ret { i32 } %.fca.0.insert 1099} 1100 1101declare <2 x i16> @llvm.mips.preceu.ph.qbl(<4 x i8>) nounwind readnone 1102 1103define { i32 } @test__builtin_mips_preceu_ph_qbr1(i32 %i0, i32 %a0.coerce) nounwind readnone { 1104entry: 1105; CHECK: preceu.ph.qbr 1106 1107 %0 = bitcast i32 %a0.coerce to <4 x i8> 1108 %1 = tail call <2 x i16> @llvm.mips.preceu.ph.qbr(<4 x i8> %0) 1109 %2 = bitcast <2 x i16> %1 to i32 1110 %.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0 1111 ret { i32 } %.fca.0.insert 1112} 1113 1114declare <2 x i16> @llvm.mips.preceu.ph.qbr(<4 x i8>) nounwind readnone 1115 1116define { i32 } @test__builtin_mips_preceu_ph_qbla1(i32 %i0, i32 %a0.coerce) nounwind readnone { 1117entry: 1118; CHECK: preceu.ph.qbla 1119 1120 %0 = bitcast i32 %a0.coerce to <4 x i8> 1121 %1 = tail call <2 x i16> @llvm.mips.preceu.ph.qbla(<4 x i8> %0) 1122 %2 = bitcast <2 x i16> %1 to i32 1123 %.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0 1124 ret { i32 } %.fca.0.insert 1125} 1126 1127declare <2 x i16> @llvm.mips.preceu.ph.qbla(<4 x i8>) nounwind readnone 1128 1129define { i32 } @test__builtin_mips_preceu_ph_qbra1(i32 %i0, i32 %a0.coerce) nounwind readnone { 1130entry: 1131; CHECK: preceu.ph.qbra 1132 1133 %0 = bitcast i32 %a0.coerce to <4 x i8> 1134 %1 = tail call <2 x i16> @llvm.mips.preceu.ph.qbra(<4 x i8> %0) 1135 %2 = bitcast <2 x i16> %1 to i32 1136 %.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0 1137 ret { i32 } %.fca.0.insert 1138} 1139 1140declare <2 x i16> @llvm.mips.preceu.ph.qbra(<4 x i8>) nounwind readnone 1141 1142define { i32 } @test__builtin_mips_repl_qb1(i32 %i0) nounwind readnone { 1143entry: 1144; CHECK: repl.qb 1145 1146 %0 = tail call <4 x i8> @llvm.mips.repl.qb(i32 127) 1147 %1 = bitcast <4 x i8> %0 to i32 1148 %.fca.0.insert = insertvalue { i32 } undef, i32 %1, 0 1149 ret { i32 } %.fca.0.insert 1150} 1151 1152declare <4 x i8> @llvm.mips.repl.qb(i32) nounwind readnone 1153 1154define { i32 } @test__builtin_mips_repl_qb2(i32 %i0, i32 %a0) nounwind readnone { 1155entry: 1156; CHECK: replv.qb 1157 1158 %0 = tail call <4 x i8> @llvm.mips.repl.qb(i32 %a0) 1159 %1 = bitcast <4 x i8> %0 to i32 1160 %.fca.0.insert = insertvalue { i32 } undef, i32 %1, 0 1161 ret { i32 } %.fca.0.insert 1162} 1163 1164define { i32 } @test__builtin_mips_repl_ph1(i32 %i0) nounwind readnone { 1165entry: 1166; CHECK: repl.ph 1167 1168 %0 = tail call <2 x i16> @llvm.mips.repl.ph(i32 0) 1169 %1 = bitcast <2 x i16> %0 to i32 1170 %.fca.0.insert = insertvalue { i32 } undef, i32 %1, 0 1171 ret { i32 } %.fca.0.insert 1172} 1173 1174declare <2 x i16> @llvm.mips.repl.ph(i32) nounwind readnone 1175 1176define { i32 } @test__builtin_mips_repl_ph2(i32 %i0, i32 %a0) nounwind readnone { 1177entry: 1178; CHECK: replv.ph 1179 1180 %0 = tail call <2 x i16> @llvm.mips.repl.ph(i32 %a0) 1181 %1 = bitcast <2 x i16> %0 to i32 1182 %.fca.0.insert = insertvalue { i32 } undef, i32 %1, 0 1183 ret { i32 } %.fca.0.insert 1184} 1185 1186define i32 @test__builtin_mips_bitrev1(i32 %i0, i32 %a0) nounwind readnone { 1187entry: 1188; CHECK: bitrev ${{[0-9]+}} 1189 1190 %0 = tail call i32 @llvm.mips.bitrev(i32 %a0) 1191 ret i32 %0 1192} 1193 1194declare i32 @llvm.mips.bitrev(i32) nounwind readnone 1195 1196define i32 @test__builtin_mips_lbux1(i32 %i0, i8* %a0, i32 %a1) nounwind readonly { 1197entry: 1198; CHECK: lbux ${{[0-9]+}} 1199 1200 %0 = tail call i32 @llvm.mips.lbux(i8* %a0, i32 %a1) 1201 ret i32 %0 1202} 1203 1204declare i32 @llvm.mips.lbux(i8*, i32) nounwind readonly 1205 1206define i32 @test__builtin_mips_lhx1(i32 %i0, i8* %a0, i32 %a1) nounwind readonly { 1207entry: 1208; CHECK: lhx ${{[0-9]+}} 1209 1210 %0 = tail call i32 @llvm.mips.lhx(i8* %a0, i32 %a1) 1211 ret i32 %0 1212} 1213 1214declare i32 @llvm.mips.lhx(i8*, i32) nounwind readonly 1215 1216define i32 @test__builtin_mips_lwx1(i32 %i0, i8* %a0, i32 %a1) nounwind readonly { 1217entry: 1218; CHECK: lwx ${{[0-9]+}} 1219 1220 %0 = tail call i32 @llvm.mips.lwx(i8* %a0, i32 %a1) 1221 ret i32 %0 1222} 1223 1224declare i32 @llvm.mips.lwx(i8*, i32) nounwind readonly 1225 1226define i32 @test__builtin_mips_wrdsp1(i32 %i0, i32 %a0) nounwind { 1227entry: 1228; CHECK: wrdsp ${{[0-9]+}} 1229; CHECK: rddsp ${{[0-9]+}} 1230 1231 tail call void @llvm.mips.wrdsp(i32 %a0, i32 31) 1232 %0 = tail call i32 @llvm.mips.rddsp(i32 31) 1233 ret i32 %0 1234} 1235 1236declare void @llvm.mips.wrdsp(i32, i32) nounwind 1237