1; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s -check-prefix=ALL \ 2; RUN: -check-prefix=M2 -check-prefix=GP32 3; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s -check-prefix=ALL \ 4; RUN: -check-prefix=32R1-R2 -check-prefix=GP32 5; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s -check-prefix=ALL \ 6; RUN: -check-prefix=32R1-R2 -check-prefix=32R2 -check-prefix=GP32 7; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s -check-prefix=ALL \ 8; RUN: -check-prefix=32R6 -check-prefix=GP32 9; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s -check-prefix=ALL \ 10; RUN: -check-prefix=M4 -check-prefix=GP64-NOT-R6 11; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s -check-prefix=ALL \ 12; RUN: -check-prefix=64R1-R2 -check-prefix=GP64-NOT-R6 13; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s -check-prefix=ALL \ 14; RUN: -check-prefix=64R1-R2 -check-prefix=GP64 -check-prefix=GP64-NOT-R6 15; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s -check-prefix=ALL \ 16; RUN: -check-prefix=64R6 17 18define signext i1 @mul_i1(i1 signext %a, i1 signext %b) { 19entry: 20; ALL-LABEL: mul_i1: 21 22 ; M2: mult $4, $5 23 ; M2: mflo $[[T0:[0-9]+]] 24 ; M2: sll $[[T0]], $[[T0]], 31 25 ; M2: sra $2, $[[T0]], 31 26 27 ; 32R1-R2: mul $[[T0:[0-9]+]], $4, $5 28 ; 32R1-R2: sll $[[T0]], $[[T0]], 31 29 ; 32R1-R2: sra $2, $[[T0]], 31 30 31 ; 32R6: mul $[[T0:[0-9]+]], $4, $5 32 ; 32R6: sll $[[T0]], $[[T0]], 31 33 ; 32R6: sra $2, $[[T0]], 31 34 35 ; M4: mult $4, $5 36 ; M4: mflo $[[T0:[0-9]+]] 37 ; M4: sll $[[T0]], $[[T0]], 31 38 ; M4: sra $2, $[[T0]], 31 39 40 ; 64R1-R2: mul $[[T0:[0-9]+]], $4, $5 41 ; 64R1-R2: sll $[[T0]], $[[T0]], 31 42 ; 64R1-R2: sra $2, $[[T0]], 31 43 44 ; 64R6: mul $[[T0:[0-9]+]], $4, $5 45 ; 64R6: sll $[[T0]], $[[T0]], 31 46 ; 64R6: sra $2, $[[T0]], 31 47 48 %r = mul i1 %a, %b 49 ret i1 %r 50} 51 52define signext i8 @mul_i8(i8 signext %a, i8 signext %b) { 53entry: 54; ALL-LABEL: mul_i8: 55 56 ; M2: mult $4, $5 57 ; M2: mflo $[[T0:[0-9]+]] 58 ; M2: sll $[[T0]], $[[T0]], 24 59 ; M2: sra $2, $[[T0]], 24 60 61 ; 32R1: mul $[[T0:[0-9]+]], $4, $5 62 ; 32R1: sll $[[T0]], $[[T0]], 24 63 ; 32R1: sra $2, $[[T0]], 24 64 65 ; 32R2: mul $[[T0:[0-9]+]], $4, $5 66 ; 32R2: seb $2, $[[T0]] 67 68 ; 32R6: mul $[[T0:[0-9]+]], $4, $5 69 ; 32R6: seb $2, $[[T0]] 70 71 ; M4: mult $4, $5 72 ; M4: mflo $[[T0:[0-9]+]] 73 ; M4: sll $[[T0]], $[[T0]], 24 74 ; M4: sra $2, $[[T0]], 24 75 76 ; 64R1: mul $[[T0:[0-9]+]], $4, $5 77 ; 64R1: sll $[[T0]], $[[T0]], 24 78 ; 64R1: sra $2, $[[T0]], 24 79 80 ; 64R2: mul $[[T0:[0-9]+]], $4, $5 81 ; 64R2: seb $2, $[[T0]] 82 83 ; 64R6: mul $[[T0:[0-9]+]], $4, $5 84 ; 64R6: seb $2, $[[T0]] 85 %r = mul i8 %a, %b 86 ret i8 %r 87} 88 89define signext i16 @mul_i16(i16 signext %a, i16 signext %b) { 90entry: 91; ALL-LABEL: mul_i16: 92 93 ; M2: mult $4, $5 94 ; M2: mflo $[[T0:[0-9]+]] 95 ; M2: sll $[[T0]], $[[T0]], 16 96 ; M2: sra $2, $[[T0]], 16 97 98 ; 32R1: mul $[[T0:[0-9]+]], $4, $5 99 ; 32R1: sll $[[T0]], $[[T0]], 16 100 ; 32R1: sra $2, $[[T0]], 16 101 102 ; 32R2: mul $[[T0:[0-9]+]], $4, $5 103 ; 32R2: seh $2, $[[T0]] 104 105 ; 32R6: mul $[[T0:[0-9]+]], $4, $5 106 ; 32R6: seh $2, $[[T0]] 107 108 ; M4: mult $4, $5 109 ; M4: mflo $[[T0:[0-9]+]] 110 ; M4: sll $[[T0]], $[[T0]], 16 111 ; M4: sra $2, $[[T0]], 16 112 113 ; 64R1: mul $[[T0:[0-9]+]], $4, $5 114 ; 64R1: sll $[[T0]], $[[T0]], 16 115 ; 64R1: sra $2, $[[T0]], 16 116 117 ; 64R2: mul $[[T0:[0-9]+]], $4, $5 118 ; 64R2: seh $2, $[[T0]] 119 120 ; 64R6: mul $[[T0:[0-9]+]], $4, $5 121 ; 64R6: seh $2, $[[T0]] 122 %r = mul i16 %a, %b 123 ret i16 %r 124} 125 126define signext i32 @mul_i32(i32 signext %a, i32 signext %b) { 127entry: 128; ALL-LABEL: mul_i32: 129 130 ; M2: mult $4, $5 131 ; M2: mflo $2 132 133 ; 32R1-R2: mul $2, $4, $5 134 ; 32R6: mul $2, $4, $5 135 136 ; 64R1-R2: mul $2, $4, $5 137 ; 64R6: mul $2, $4, $5 138 %r = mul i32 %a, %b 139 ret i32 %r 140} 141 142define signext i64 @mul_i64(i64 signext %a, i64 signext %b) { 143entry: 144; ALL-LABEL: mul_i64: 145 146 ; M2: mult $4, $7 147 ; M2: mflo $[[T0:[0-9]+]] 148 ; M2: mult $5, $6 149 ; M2: mflo $[[T1:[0-9]+]] 150 ; M2: multu $5, $7 151 ; M2: mflo $3 152 ; M2: mfhi $4 153 ; M2: addu $[[T2:[0-9]+]], $4, $[[T1]] 154 ; M2: addu $2, $[[T2]], $[[T0]] 155 156 ; 32R1-R2: multu $5, $7 157 ; 32R1-R2: mflo $3 158 ; 32R1-R2: mfhi $[[T0:[0-9]+]] 159 ; 32R1-R2: mul $[[T1:[0-9]+]], $4, $7 160 ; 32R1-R2: mul $[[T2:[0-9]+]], $5, $6 161 ; 32R1-R2: addu $[[T0]], $[[T0]], $[[T2:[0-9]+]] 162 ; 32R1-R2: addu $2, $[[T0]], $[[T1]] 163 164 ; 32R6: mul $[[T0:[0-9]+]], $5, $6 165 ; 32R6: muhu $[[T1:[0-9]+]], $5, $7 166 ; 32R6: addu $[[T0]], $[[T1]], $[[T0]] 167 ; 32R6: mul $[[T2:[0-9]+]], $4, $7 168 ; 32R6: addu $2, $[[T0]], $[[T2]] 169 ; 32R6: mul $3, $5, $7 170 171 ; M4: dmult $4, $5 172 ; M4: mflo $2 173 174 ; 64R1-R2: dmult $4, $5 175 ; 64R1-R2: mflo $2 176 177 ; 64R6: dmul $2, $4, $5 178 179 %r = mul i64 %a, %b 180 ret i64 %r 181} 182 183define signext i128 @mul_i128(i128 signext %a, i128 signext %b) { 184entry: 185; ALL-LABEL: mul_i128: 186 187 ; GP32: lw $25, %call16(__multi3)($gp) 188 189 ; GP64-NOT-R6: dmult $4, $7 190 ; GP64-NOT-R6: mflo $[[T0:[0-9]+]] 191 ; GP64-NOT-R6: dmult $5, $6 192 ; GP64-NOT-R6: mflo $[[T1:[0-9]+]] 193 ; GP64-NOT-R6: dmultu $5, $7 194 ; GP64-NOT-R6: mflo $3 195 ; GP64-NOT-R6: mfhi $[[T2:[0-9]+]] 196 ; GP64-NOT-R6: daddu $[[T3:[0-9]+]], $[[T2]], $[[T1]] 197 ; GP64-NOT-R6: daddu $2, $[[T3:[0-9]+]], $[[T0]] 198 199 ; 64R6: dmul $[[T0:[0-9]+]], $5, $6 200 ; 64R6: dmuhu $[[T1:[0-9]+]], $5, $7 201 ; 64R6: daddu $[[T2:[0-9]+]], $[[T1]], $[[T0]] 202 ; 64R6: dmul $[[T3:[0-9]+]], $4, $7 203 ; 64R6: daddu $2, $[[T2]], $[[T3]] 204 ; 64R6: dmul $3, $5, $7 205 206 %r = mul i128 %a, %b 207 ret i128 %r 208} 209