1; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \
2; RUN:    -check-prefix=ALL -check-prefix=M2 -check-prefix=M2-M3
3; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \
4; RUN:    -check-prefix=ALL -check-prefix=CMOV \
5; RUN:    -check-prefix=CMOV-32 -check-prefix=CMOV-32R1
6; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \
7; RUN:    -check-prefix=ALL -check-prefix=CMOV \
8; RUN:    -check-prefix=CMOV-32 -check-prefix=CMOV-32R2
9; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \
10; RUN:    -check-prefix=ALL -check-prefix=SEL -check-prefix=SEL-32
11; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \
12; RUN:    -check-prefix=ALL -check-prefix=M3 -check-prefix=M2-M3
13; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \
14; RUN:    -check-prefix=ALL -check-prefix=CMOV -check-prefix=CMOV-64
15; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \
16; RUN:    -check-prefix=ALL -check-prefix=CMOV -check-prefix=CMOV-64
17; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \
18; RUN:    -check-prefix=ALL -check-prefix=CMOV -check-prefix=CMOV-64
19; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \
20; RUN:    -check-prefix=ALL -check-prefix=SEL -check-prefix=SEL-64
21
22define signext i1 @tst_select_i1_i1(i1 signext %s,
23                                    i1 signext %x, i1 signext %y) {
24entry:
25  ; ALL-LABEL: tst_select_i1_i1:
26
27  ; M2-M3:  andi    $[[T0:[0-9]+]], $4, 1
28  ; M2-M3:  bnez    $[[T0]], $[[BB0:BB[0-9_]+]]
29  ; M2-M3:  nop
30  ; M2-M3:  move    $5, $6
31  ; M2-M3:  $[[BB0]]:
32  ; M2-M3:  jr      $ra
33  ; M2-M3:  move    $2, $5
34
35  ; CMOV:   andi    $[[T0:[0-9]+]], $4, 1
36  ; CMOV:   movn    $6, $5, $[[T0]]
37  ; CMOV:   move    $2, $6
38
39  ; SEL:    andi    $[[T0:[0-9]+]], $4, 1
40  ; SEL:    seleqz  $[[T1:[0-9]+]], $6, $[[T0]]
41  ; SEL:    selnez  $[[T2:[0-9]+]], $5, $[[T0]]
42  ; SEL:    or      $2, $[[T2]], $[[T1]]
43  %r = select i1 %s, i1 %x, i1 %y
44  ret i1 %r
45}
46
47define signext i8 @tst_select_i1_i8(i1 signext %s,
48                                    i8 signext %x, i8 signext %y) {
49entry:
50  ; ALL-LABEL: tst_select_i1_i8:
51
52  ; M2-M3:  andi    $[[T0:[0-9]+]], $4, 1
53  ; M2-M3:  bnez    $[[T0]], $[[BB0:BB[0-9_]+]]
54  ; M2-M3:  nop
55  ; M2-M3:  move    $5, $6
56  ; M2-M3:  $[[BB0]]:
57  ; M2-M3:  jr      $ra
58  ; M2-M3:  move    $2, $5
59
60  ; CMOV:   andi    $[[T0:[0-9]+]], $4, 1
61  ; CMOV:   movn    $6, $5, $[[T0]]
62  ; CMOV:   move    $2, $6
63
64  ; SEL:    andi    $[[T0:[0-9]+]], $4, 1
65  ; SEL:    seleqz  $[[T1:[0-9]+]], $6, $[[T0]]
66  ; SEL:    selnez  $[[T2:[0-9]+]], $5, $[[T0]]
67  ; SEL:    or      $2, $[[T2]], $[[T1]]
68  %r = select i1 %s, i8 %x, i8 %y
69  ret i8 %r
70}
71
72define signext i32 @tst_select_i1_i32(i1 signext %s,
73                                      i32 signext %x, i32 signext %y) {
74entry:
75  ; ALL-LABEL: tst_select_i1_i32:
76
77  ; M2-M3:  andi    $[[T0:[0-9]+]], $4, 1
78  ; M2-M3:  bnez    $[[T0]], $[[BB0:BB[0-9_]+]]
79  ; M2-M3:  nop
80  ; M2-M3:  move    $5, $6
81  ; M2-M3:  $[[BB0]]:
82  ; M2-M3:  jr      $ra
83  ; M2-M3:  move    $2, $5
84
85  ; CMOV:   andi    $[[T0:[0-9]+]], $4, 1
86  ; CMOV:   movn    $6, $5, $[[T0]]
87  ; CMOV:   move    $2, $6
88
89  ; SEL:    andi    $[[T0:[0-9]+]], $4, 1
90  ; SEL:    seleqz  $[[T1:[0-9]+]], $6, $[[T0]]
91  ; SEL:    selnez  $[[T2:[0-9]+]], $5, $[[T0]]
92  ; SEL:    or      $2, $[[T2]], $[[T1]]
93  %r = select i1 %s, i32 %x, i32 %y
94  ret i32 %r
95}
96
97define signext i64 @tst_select_i1_i64(i1 signext %s,
98                                      i64 signext %x, i64 signext %y) {
99entry:
100  ; ALL-LABEL: tst_select_i1_i64:
101
102  ; M2:     andi    $[[T0:[0-9]+]], $4, 1
103  ; M2:     bnez    $[[T0]], $[[BB0:BB[0-9_]+]]
104  ; M2:     nop
105  ; M2:     lw      $[[T1:[0-9]+]], 16($sp)
106  ; M2:     $[[BB0]]:
107  ; FIXME: This branch is redundant
108  ; M2:     bnez    $[[T0]], $[[BB1:BB[0-9_]+]]
109  ; M2:     nop
110  ; M2:     lw      $[[T2:[0-9]+]], 20($sp)
111  ; M2:     $[[BB1]]:
112  ; M2:     move    $2, $[[T1]]
113  ; M2:     jr      $ra
114  ; M2:     move    $3, $[[T2]]
115
116  ; CMOV-32:    andi    $[[T0:[0-9]+]], $4, 1
117  ; CMOV-32:    lw      $2, 16($sp)
118  ; CMOV-32:    movn    $2, $6, $[[T0]]
119  ; CMOV-32:    lw      $3, 20($sp)
120  ; CMOV-32:    movn    $3, $7, $[[T0]]
121
122  ; SEL-32:     andi    $[[T0:[0-9]+]], $4, 1
123  ; SEL-32:     selnez  $[[T1:[0-9]+]], $6, $[[T0]]
124  ; SEL-32:     lw      $[[T2:[0-9]+]], 16($sp)
125  ; SEL-32:     seleqz  $[[T3:[0-9]+]], $[[T2]], $[[T0]]
126  ; SEL-32:     or      $2, $[[T1]], $[[T3]]
127  ; SEL-32:     selnez  $[[T4:[0-9]+]], $7, $[[T0]]
128  ; SEL-32:     lw      $[[T5:[0-9]+]], 20($sp)
129  ; SEL-32:     seleqz  $[[T6:[0-9]+]], $[[T5]], $[[T0]]
130  ; SEL-32:     or      $3, $[[T4]], $[[T6]]
131
132  ; M3:         andi    $[[T0:[0-9]+]], $4, 1
133  ; M3:         bnez    $[[T0]], $[[BB0:BB[0-9_]+]]
134  ; M3:         nop
135  ; M3:         move    $5, $6
136  ; M3:         $[[BB0]]:
137  ; M3:         jr      $ra
138  ; M3:         move    $2, $5
139
140  ; CMOV-64:    andi    $[[T0:[0-9]+]], $4, 1
141  ; CMOV-64:    movn    $6, $5, $[[T0]]
142  ; CMOV-64:    move    $2, $6
143
144  ; SEL-64:     andi    $[[T0:[0-9]+]], $4, 1
145  ; FIXME: This shift is redundant
146  ; SEL-64:     sll     $[[T0]], $[[T0]], 0
147  ; SEL-64:     seleqz  $[[T1:[0-9]+]], $6, $[[T0]]
148  ; SEL-64:     selnez  $[[T0]], $5, $[[T0]]
149  ; SEL-64:     or      $2, $[[T0]], $[[T1]]
150  %r = select i1 %s, i64 %x, i64 %y
151  ret i64 %r
152}
153
154define float @tst_select_i1_float(i1 signext %s, float %x, float %y) {
155entry:
156  ; ALL-LABEL: tst_select_i1_float:
157
158  ; M2-M3:      andi    $[[T0:[0-9]+]], $4, 1
159  ; M2-M3:      bnez    $[[T0]], $[[BB0:BB[0-9_]+]]
160  ; M2-M3:      nop
161  ; M2:         jr      $ra
162  ; M2:         mtc1    $6, $f0
163  ; M3:         mov.s   $f13, $f14
164  ; M2-M3:      $[[BB0]]:
165  ; M2-M3:      jr      $ra
166  ; M2:         mtc1    $5, $f0
167  ; M3:         mov.s   $f0, $f13
168
169  ; CMOV-32:    mtc1    $6, $f0
170  ; CMOV-32:    mtc1    $5, $f1
171  ; CMOV-32:    andi    $[[T0:[0-9]+]], $4, 1
172  ; CMOV-32:    movn.s  $f0, $f1, $[[T0]]
173
174  ; SEL-32:     mtc1    $5, $[[F0:f[0-9]+]]
175  ; SEL-32:     mtc1    $6, $[[F1:f[0-9]+]]
176  ; SEL-32:     mtc1    $4, $f0
177  ; SEL-32:     sel.s   $f0, $[[F1]], $[[F0]]
178
179  ; CMOV-64:    andi    $[[T0:[0-9]+]], $4, 1
180  ; CMOV-64:    movn.s  $f14, $f13, $[[T0]]
181  ; CMOV-64:    mov.s   $f0, $f14
182
183  ; SEL-64:     mtc1    $4, $f0
184  ; SEL-64:     sel.s   $f0, $f14, $f13
185  %r = select i1 %s, float %x, float %y
186  ret float %r
187}
188
189define float @tst_select_i1_float_reordered(float %x, float %y,
190                                            i1 signext %s) {
191entry:
192  ; ALL-LABEL: tst_select_i1_float_reordered:
193
194  ; M2-M3:      andi    $[[T0:[0-9]+]], $6, 1
195  ; M2-M3:      bnez    $[[T0]], $[[BB0:BB[0-9_]+]]
196  ; M2-M3:      nop
197  ; M2:         mov.s   $f12, $f14
198  ; M3:         mov.s   $f12, $f13
199  ; M2-M3:      $[[BB0]]:
200  ; M2-M3:      jr      $ra
201  ; M2-M3:      mov.s   $f0, $f12
202
203  ; CMOV-32:    andi    $[[T0:[0-9]+]], $6, 1
204  ; CMOV-32:    movn.s  $f14, $f12, $[[T0]]
205  ; CMOV-32:    mov.s   $f0, $f14
206
207  ; SEL-32:     mtc1    $6, $f0
208  ; SEL-32:     sel.s   $f0, $f14, $f12
209
210  ; CMOV-64:    andi    $[[T0:[0-9]+]], $6, 1
211  ; CMOV-64:    movn.s  $f13, $f12, $[[T0]]
212  ; CMOV-64:    mov.s   $f0, $f13
213
214  ; SEL-64:     mtc1    $6, $f0
215  ; SEL-64:     sel.s   $f0, $f13, $f12
216  %r = select i1 %s, float %x, float %y
217  ret float %r
218}
219
220define double @tst_select_i1_double(i1 signext %s, double %x, double %y) {
221entry:
222  ; ALL-LABEL: tst_select_i1_double:
223
224  ; M2:         andi    $[[T0:[0-9]+]], $4, 1
225  ; M2:         bnez    $[[T0]], $[[BB0:BB[0-9_]+]]
226  ; M2:         nop
227  ; M2:         ldc1    $f0, 16($sp)
228  ; M2:         jr      $ra
229  ; M2:         nop
230  ; M2:         $[[BB0]]:
231  ; M2:         mtc1    $7, $f0
232  ; M2:         jr      $ra
233  ; M2:         mtc1    $6, $f1
234
235  ; CMOV-32:    mtc1    $7, $[[F0:f[0-9]+]]
236  ; CMOV-32R1:  mtc1    $6, $f{{[0-9]+}}
237  ; CMOV-32R2   mthc1   $6, $[[F0]]
238  ; CMOV-32:    andi    $[[T0:[0-9]+]], $4, 1
239  ; CMOV-32:    ldc1    $f0, 16($sp)
240  ; CMOV-32:    movn.d  $f0, $[[F0]], $[[T0]]
241
242  ; SEL-32:     mtc1    $7, $[[F0:f[0-9]+]]
243  ; SEL-32:     mthc1   $6, $[[F0]]
244  ; SEL-32:     ldc1    $[[F1:f[0-9]+]], 16($sp)
245  ; SEL-32:     mtc1    $4, $f0
246  ; SEL-32:     sel.d   $f0, $[[F1]], $[[F0]]
247
248  ; M3:         andi    $[[T0:[0-9]+]], $4, 1
249  ; M3:         bnez    $[[T0]], $[[BB0:BB[0-9_]+]]
250  ; M3:         nop
251  ; M3:         mov.d   $f13, $f14
252  ; M3:         $[[BB0]]:
253  ; M3:         jr      $ra
254  ; M3:         mov.d   $f0, $f13
255
256  ; CMOV-64:    andi    $[[T0:[0-9]+]], $4, 1
257  ; CMOV-64:    movn.d  $f14, $f13, $[[T0]]
258  ; CMOV-64:    mov.d   $f0, $f14
259
260  ; SEL-64:     mtc1    $4, $f0
261  ; SEL-64:     sel.d   $f0, $f14, $f13
262  %r = select i1 %s, double %x, double %y
263  ret double %r
264}
265
266define double @tst_select_i1_double_reordered(double %x, double %y,
267                                              i1 signext %s) {
268entry:
269  ; ALL-LABEL: tst_select_i1_double_reordered:
270
271  ; M2:         lw      $[[T0:[0-9]+]], 16($sp)
272  ; M2:         andi    $[[T1:[0-9]+]], $[[T0]], 1
273  ; M2:         bnez    $[[T1]], $[[BB0:BB[0-9_]+]]
274  ; M2:         nop
275  ; M2:         mov.d   $f12, $f14
276  ; M2:         $[[BB0]]:
277  ; M2:         jr      $ra
278  ; M2:         mov.d   $f0, $f12
279
280  ; CMOV-32:    lw      $[[T0:[0-9]+]], 16($sp)
281  ; CMOV-32:    andi    $[[T1:[0-9]+]], $[[T0]], 1
282  ; CMOV-32:    movn.d  $f14, $f12, $[[T1]]
283  ; CMOV-32:    mov.d   $f0, $f14
284
285  ; SEL-32:     lw      $[[T0:[0-9]+]], 16($sp)
286  ; SEL-32:     mtc1    $[[T0]], $f0
287  ; SEL-32:     sel.d   $f0, $f14, $f12
288
289  ; M3:         andi    $[[T0:[0-9]+]], $6, 1
290  ; M3:         bnez    $[[T0]], $[[BB0:BB[0-9_]+]]
291  ; M3:         nop
292  ; M3:         mov.d   $f12, $f13
293  ; M3:         $[[BB0]]:
294  ; M3:         jr      $ra
295  ; M3:         mov.d   $f0, $f12
296
297  ; CMOV-64:    andi    $[[T0:[0-9]+]], $6, 1
298  ; CMOV-64:    movn.d  $f13, $f12, $[[T0]]
299  ; CMOV-64:    mov.d   $f0, $f13
300
301  ; SEL-64:     mtc1    $6, $f0
302  ; SEL-64:     sel.d   $f0, $f13, $f12
303  %r = select i1 %s, double %x, double %y
304  ret double %r
305}
306
307define float @tst_select_fcmp_olt_float(float %x, float %y) {
308entry:
309  ; ALL-LABEL: tst_select_fcmp_olt_float:
310
311  ; M2:         c.olt.s   $f12, $f14
312  ; M3:         c.olt.s   $f12, $f13
313  ; M2-M3:      bc1t      $[[BB0:BB[0-9_]+]]
314  ; M2-M3:      nop
315  ; M2:         mov.s     $f12, $f14
316  ; M3:         mov.s     $f12, $f13
317  ; M2-M3:      $[[BB0]]:
318  ; M2-M3:      jr        $ra
319  ; M2-M3:      mov.s     $f0, $f12
320
321  ; CMOV-32:    c.olt.s   $f12, $f14
322  ; CMOV-32:    movt.s    $f14, $f12, $fcc0
323  ; CMOV-32:    mov.s     $f0, $f14
324
325  ; SEL-32:     cmp.lt.s  $f0, $f12, $f14
326  ; SEL-32:     sel.s     $f0, $f14, $f12
327
328  ; CMOV-64:    c.olt.s   $f12, $f13
329  ; CMOV-64:    movt.s    $f13, $f12, $fcc0
330  ; CMOV-64:    mov.s     $f0, $f13
331
332  ; SEL-64:     cmp.lt.s  $f0, $f12, $f13
333  ; SEL-64:     sel.s     $f0, $f13, $f12
334  %s = fcmp olt float %x, %y
335  %r = select i1 %s, float %x, float %y
336  ret float %r
337}
338
339define float @tst_select_fcmp_ole_float(float %x, float %y) {
340entry:
341  ; ALL-LABEL: tst_select_fcmp_ole_float:
342
343  ; M2:         c.ole.s   $f12, $f14
344  ; M3:         c.ole.s   $f12, $f13
345  ; M2-M3:      bc1t      $[[BB0:BB[0-9_]+]]
346  ; M2-M3:      nop
347  ; M2:         mov.s     $f12, $f14
348  ; M3:         mov.s     $f12, $f13
349  ; M2-M3:      $[[BB0]]:
350  ; M2-M3:      jr        $ra
351  ; M2-M3:      mov.s     $f0, $f12
352
353  ; CMOV-32:    c.ole.s   $f12, $f14
354  ; CMOV-32:    movt.s    $f14, $f12, $fcc0
355  ; CMOV-32:    mov.s     $f0, $f14
356
357  ; SEL-32:     cmp.le.s  $f0, $f12, $f14
358  ; SEL-32:     sel.s     $f0, $f14, $f12
359
360  ; CMOV-64:    c.ole.s   $f12, $f13
361  ; CMOV-64:    movt.s    $f13, $f12, $fcc0
362  ; CMOV-64:    mov.s     $f0, $f13
363
364  ; SEL-64:     cmp.le.s  $f0, $f12, $f13
365  ; SEL-64:     sel.s     $f0, $f13, $f12
366  %s = fcmp ole float %x, %y
367  %r = select i1 %s, float %x, float %y
368  ret float %r
369}
370
371define float @tst_select_fcmp_ogt_float(float %x, float %y) {
372entry:
373  ; ALL-LABEL: tst_select_fcmp_ogt_float:
374
375  ; M2:         c.ule.s   $f12, $f14
376  ; M3:         c.ule.s   $f12, $f13
377  ; M2-M3:      bc1f      $[[BB0:BB[0-9_]+]]
378  ; M2-M3:      nop
379  ; M2:         mov.s     $f12, $f14
380  ; M3:         mov.s     $f12, $f13
381  ; M2-M3:      $[[BB0]]:
382  ; M2-M3:      jr        $ra
383  ; M2-M3:      mov.s     $f0, $f12
384
385  ; CMOV-32:    c.ule.s   $f12, $f14
386  ; CMOV-32:    movf.s    $f14, $f12, $fcc0
387  ; CMOV-32:    mov.s     $f0, $f14
388
389  ; SEL-32:     cmp.lt.s  $f0, $f14, $f12
390  ; SEL-32:     sel.s     $f0, $f14, $f12
391
392  ; CMOV-64:    c.ule.s   $f12, $f13
393  ; CMOV-64:    movf.s    $f13, $f12, $fcc0
394  ; CMOV-64:    mov.s     $f0, $f13
395
396  ; SEL-64:     cmp.lt.s  $f0, $f13, $f12
397  ; SEL-64:     sel.s     $f0, $f13, $f12
398  %s = fcmp ogt float %x, %y
399  %r = select i1 %s, float %x, float %y
400  ret float %r
401}
402
403define float @tst_select_fcmp_oge_float(float %x, float %y) {
404entry:
405  ; ALL-LABEL: tst_select_fcmp_oge_float:
406
407  ; M2:         c.ult.s   $f12, $f14
408  ; M3:         c.ult.s   $f12, $f13
409  ; M2-M3:      bc1f      $[[BB0:BB[0-9_]+]]
410  ; M2-M3:      nop
411  ; M2:         mov.s     $f12, $f14
412  ; M3:         mov.s     $f12, $f13
413  ; M2-M3:      $[[BB0]]:
414  ; M2-M3:      jr        $ra
415  ; M2-M3:      mov.s     $f0, $f12
416
417  ; CMOV-32:    c.ult.s   $f12, $f14
418  ; CMOV-32:    movf.s    $f14, $f12, $fcc0
419  ; CMOV-32:    mov.s     $f0, $f14
420
421  ; SEL-32:     cmp.le.s  $f0, $f14, $f12
422  ; SEL-32:     sel.s     $f0, $f14, $f12
423
424  ; CMOV-64:    c.ult.s   $f12, $f13
425  ; CMOV-64:    movf.s    $f13, $f12, $fcc0
426  ; CMOV-64:    mov.s     $f0, $f13
427
428  ; SEL-64:     cmp.le.s  $f0, $f13, $f12
429  ; SEL-64:     sel.s     $f0, $f13, $f12
430  %s = fcmp oge float %x, %y
431  %r = select i1 %s, float %x, float %y
432  ret float %r
433}
434
435define float @tst_select_fcmp_oeq_float(float %x, float %y) {
436entry:
437  ; ALL-LABEL: tst_select_fcmp_oeq_float:
438
439  ; M2:         c.eq.s    $f12, $f14
440  ; M3:         c.eq.s    $f12, $f13
441  ; M2-M3:      bc1t      $[[BB0:BB[0-9_]+]]
442  ; M2-M3:      nop
443  ; M2:         mov.s     $f12, $f14
444  ; M3:         mov.s     $f12, $f13
445  ; M2-M3:      $[[BB0]]:
446  ; M2-M3:      jr        $ra
447  ; M2-M3:      mov.s     $f0, $f12
448
449  ; CMOV-32:    c.eq.s    $f12, $f14
450  ; CMOV-32:    movt.s    $f14, $f12, $fcc0
451  ; CMOV-32:    mov.s     $f0, $f14
452
453  ; SEL-32:     cmp.eq.s  $f0, $f12, $f14
454  ; SEL-32:     sel.s     $f0, $f14, $f12
455
456  ; CMOV-64:    c.eq.s    $f12, $f13
457  ; CMOV-64:    movt.s    $f13, $f12, $fcc0
458  ; CMOV-64:    mov.s     $f0, $f13
459
460  ; SEL-64:     cmp.eq.s  $f0, $f12, $f13
461  ; SEL-64:     sel.s     $f0, $f13, $f12
462  %s = fcmp oeq float %x, %y
463  %r = select i1 %s, float %x, float %y
464  ret float %r
465}
466
467define float @tst_select_fcmp_one_float(float %x, float %y) {
468entry:
469  ; ALL-LABEL: tst_select_fcmp_one_float:
470
471  ; M2:         c.ueq.s   $f12, $f14
472  ; M3:         c.ueq.s   $f12, $f13
473  ; M2-M3:      bc1f      $[[BB0:BB[0-9_]+]]
474  ; M2-M3:      nop
475  ; M2:         mov.s     $f12, $f14
476  ; M3:         mov.s     $f12, $f13
477  ; M2-M3:      $[[BB0]]:
478  ; M2-M3:      jr        $ra
479  ; M2-M3:      mov.s     $f0, $f12
480
481  ; CMOV-32:    c.ueq.s   $f12, $f14
482  ; CMOV-32:    movf.s    $f14, $f12, $fcc0
483  ; CMOV-32:    mov.s     $f0, $f14
484
485  ; SEL-32:     cmp.ueq.s $f0, $f12, $f14
486  ; SEL-32:     mfc1      $[[T0:[0-9]+]], $f0
487  ; SEL-32:     not       $[[T0]], $[[T0]]
488  ; SEL-32:     mtc1      $[[T0:[0-9]+]], $f0
489  ; SEL-32:     sel.s     $f0, $f14, $f12
490
491  ; CMOV-64:    c.ueq.s   $f12, $f13
492  ; CMOV-64:    movf.s    $f13, $f12, $fcc0
493  ; CMOV-64:    mov.s     $f0, $f13
494
495  ; SEL-64:     cmp.ueq.s $f0, $f12, $f13
496  ; SEL-64:     mfc1      $[[T0:[0-9]+]], $f0
497  ; SEL-64:     not       $[[T0]], $[[T0]]
498  ; SEL-64:     mtc1      $[[T0:[0-9]+]], $f0
499  ; SEL-64:     sel.s     $f0, $f13, $f12
500
501  %s = fcmp one float %x, %y
502  %r = select i1 %s, float %x, float %y
503  ret float %r
504}
505
506define double @tst_select_fcmp_olt_double(double %x, double %y) {
507entry:
508  ; ALL-LABEL: tst_select_fcmp_olt_double:
509
510  ; M2:         c.olt.d   $f12, $f14
511  ; M3:         c.olt.d   $f12, $f13
512  ; M2-M3:      bc1t      $[[BB0:BB[0-9_]+]]
513  ; M2-M3:      nop
514  ; M2:         mov.d     $f12, $f14
515  ; M3:         mov.d     $f12, $f13
516  ; M2-M3:      $[[BB0]]:
517  ; M2-M3:      jr        $ra
518  ; M2-M3:      mov.d     $f0, $f12
519
520  ; CMOV-32:    c.olt.d   $f12, $f14
521  ; CMOV-32:    movt.d    $f14, $f12, $fcc0
522  ; CMOV-32:    mov.d     $f0, $f14
523
524  ; SEL-32:     cmp.lt.d  $f0, $f12, $f14
525  ; SEL-32:     sel.d     $f0, $f14, $f12
526
527  ; CMOV-64:    c.olt.d   $f12, $f13
528  ; CMOV-64:    movt.d    $f13, $f12, $fcc0
529  ; CMOV-64:    mov.d     $f0, $f13
530
531  ; SEL-64:     cmp.lt.d  $f0, $f12, $f13
532  ; SEL-64:     sel.d     $f0, $f13, $f12
533  %s = fcmp olt double %x, %y
534  %r = select i1 %s, double %x, double %y
535  ret double %r
536}
537
538define double @tst_select_fcmp_ole_double(double %x, double %y) {
539entry:
540  ; ALL-LABEL: tst_select_fcmp_ole_double:
541
542  ; M2:         c.ole.d   $f12, $f14
543  ; M3:         c.ole.d   $f12, $f13
544  ; M2-M3:      bc1t      $[[BB0:BB[0-9_]+]]
545  ; M2-M3:      nop
546  ; M2:         mov.d     $f12, $f14
547  ; M3:         mov.d     $f12, $f13
548  ; M2-M3:      $[[BB0]]:
549  ; M2-M3:      jr        $ra
550  ; M2-M3:      mov.d     $f0, $f12
551
552  ; CMOV-32:    c.ole.d   $f12, $f14
553  ; CMOV-32:    movt.d    $f14, $f12, $fcc0
554  ; CMOV-32:    mov.d     $f0, $f14
555
556  ; SEL-32:     cmp.le.d  $f0, $f12, $f14
557  ; SEL-32:     sel.d     $f0, $f14, $f12
558
559  ; CMOV-64:    c.ole.d   $f12, $f13
560  ; CMOV-64:    movt.d    $f13, $f12, $fcc0
561  ; CMOV-64:    mov.d     $f0, $f13
562
563  ; SEL-64:     cmp.le.d  $f0, $f12, $f13
564  ; SEL-64:     sel.d     $f0, $f13, $f12
565  %s = fcmp ole double %x, %y
566  %r = select i1 %s, double %x, double %y
567  ret double %r
568}
569
570define double @tst_select_fcmp_ogt_double(double %x, double %y) {
571entry:
572  ; ALL-LABEL: tst_select_fcmp_ogt_double:
573
574  ; M2:         c.ule.d   $f12, $f14
575  ; M3:         c.ule.d   $f12, $f13
576  ; M2-M3:      bc1f      $[[BB0:BB[0-9_]+]]
577  ; M2-M3:      nop
578  ; M2:         mov.d     $f12, $f14
579  ; M3:         mov.d     $f12, $f13
580  ; M2-M3:      $[[BB0]]:
581  ; M2-M3:      jr        $ra
582  ; M2-M3:      mov.d     $f0, $f12
583
584  ; CMOV-32:    c.ule.d   $f12, $f14
585  ; CMOV-32:    movf.d    $f14, $f12, $fcc0
586  ; CMOV-32:    mov.d     $f0, $f14
587
588  ; SEL-32:     cmp.lt.d  $f0, $f14, $f12
589  ; SEL-32:     sel.d     $f0, $f14, $f12
590
591  ; CMOV-64:    c.ule.d   $f12, $f13
592  ; CMOV-64:    movf.d    $f13, $f12, $fcc0
593  ; CMOV-64:    mov.d     $f0, $f13
594
595  ; SEL-64:     cmp.lt.d  $f0, $f13, $f12
596  ; SEL-64:     sel.d     $f0, $f13, $f12
597  %s = fcmp ogt double %x, %y
598  %r = select i1 %s, double %x, double %y
599  ret double %r
600}
601
602define double @tst_select_fcmp_oge_double(double %x, double %y) {
603entry:
604  ; ALL-LABEL: tst_select_fcmp_oge_double:
605
606  ; M2:         c.ult.d   $f12, $f14
607  ; M3:         c.ult.d   $f12, $f13
608  ; M2-M3:      bc1f      $[[BB0:BB[0-9_]+]]
609  ; M2-M3:      nop
610  ; M2:         mov.d     $f12, $f14
611  ; M3:         mov.d     $f12, $f13
612  ; M2-M3:      $[[BB0]]:
613  ; M2-M3:      jr        $ra
614  ; M2-M3:      mov.d     $f0, $f12
615
616  ; CMOV-32:    c.ult.d   $f12, $f14
617  ; CMOV-32:    movf.d    $f14, $f12, $fcc0
618  ; CMOV-32:    mov.d     $f0, $f14
619
620  ; SEL-32:     cmp.le.d  $f0, $f14, $f12
621  ; SEL-32:     sel.d     $f0, $f14, $f12
622
623  ; CMOV-64:    c.ult.d   $f12, $f13
624  ; CMOV-64:    movf.d    $f13, $f12, $fcc0
625  ; CMOV-64:    mov.d     $f0, $f13
626
627  ; SEL-64:     cmp.le.d  $f0, $f13, $f12
628  ; SEL-64:     sel.d     $f0, $f13, $f12
629  %s = fcmp oge double %x, %y
630  %r = select i1 %s, double %x, double %y
631  ret double %r
632}
633
634define double @tst_select_fcmp_oeq_double(double %x, double %y) {
635entry:
636  ; ALL-LABEL: tst_select_fcmp_oeq_double:
637
638  ; M2:         c.eq.d    $f12, $f14
639  ; M3:         c.eq.d    $f12, $f13
640  ; M2-M3:      bc1t      $[[BB0:BB[0-9_]+]]
641  ; M2-M3:      nop
642  ; M2:         mov.d     $f12, $f14
643  ; M3:         mov.d     $f12, $f13
644  ; M2-M3:      $[[BB0]]:
645  ; M2-M3:      jr        $ra
646  ; M2-M3:      mov.d     $f0, $f12
647
648  ; CMOV-32:    c.eq.d    $f12, $f14
649  ; CMOV-32:    movt.d    $f14, $f12, $fcc0
650  ; CMOV-32:    mov.d     $f0, $f14
651
652  ; SEL-32:     cmp.eq.d  $f0, $f12, $f14
653  ; SEL-32:     sel.d     $f0, $f14, $f12
654
655  ; CMOV-64:    c.eq.d    $f12, $f13
656  ; CMOV-64:    movt.d    $f13, $f12, $fcc0
657  ; CMOV-64:    mov.d     $f0, $f13
658
659  ; SEL-64:     cmp.eq.d  $f0, $f12, $f13
660  ; SEL-64:     sel.d     $f0, $f13, $f12
661  %s = fcmp oeq double %x, %y
662  %r = select i1 %s, double %x, double %y
663  ret double %r
664}
665
666define double @tst_select_fcmp_one_double(double %x, double %y) {
667entry:
668  ; ALL-LABEL: tst_select_fcmp_one_double:
669
670  ; M2:         c.ueq.d   $f12, $f14
671  ; M3:         c.ueq.d   $f12, $f13
672  ; M2-M3:      bc1f      $[[BB0:BB[0-9_]+]]
673  ; M2-M3:      nop
674  ; M2:         mov.d     $f12, $f14
675  ; M3:         mov.d     $f12, $f13
676  ; M2-M3:      $[[BB0]]:
677  ; M2-M3:      jr        $ra
678  ; M2-M3:      mov.d     $f0, $f12
679
680  ; CMOV-32:    c.ueq.d   $f12, $f14
681  ; CMOV-32:    movf.d    $f14, $f12, $fcc0
682  ; CMOV-32:    mov.d     $f0, $f14
683
684  ; SEL-32:     cmp.ueq.d $f0, $f12, $f14
685  ; SEL-32:     mfc1      $[[T0:[0-9]+]], $f0
686  ; SEL-32:     not       $[[T0]], $[[T0]]
687  ; SEL-32:     mtc1      $[[T0:[0-9]+]], $f0
688  ; SEL-32:     sel.d     $f0, $f14, $f12
689
690  ; CMOV-64:    c.ueq.d   $f12, $f13
691  ; CMOV-64:    movf.d    $f13, $f12, $fcc0
692  ; CMOV-64:    mov.d     $f0, $f13
693
694  ; SEL-64:     cmp.ueq.d $f0, $f12, $f13
695  ; SEL-64:     mfc1      $[[T0:[0-9]+]], $f0
696  ; SEL-64:     not       $[[T0]], $[[T0]]
697  ; SEL-64:     mtc1      $[[T0:[0-9]+]], $f0
698  ; SEL-64:     sel.d     $f0, $f13, $f12
699  %s = fcmp one double %x, %y
700  %r = select i1 %s, double %x, double %y
701  ret double %r
702}
703