1; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \
2; RUN:    -check-prefix=ALL -check-prefix=NOT-R2-R6 -check-prefix=GP32
3; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \
4; RUN:    -check-prefix=ALL -check-prefix=NOT-R2-R6 -check-prefix=GP32
5; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \
6; RUN:    -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP32
7; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \
8; RUN:    -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP32
9; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \
10; RUN:    -check-prefix=ALL -check-prefix=NOT-R2-R6 -check-prefix=GP64
11; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \
12; RUN:    -check-prefix=ALL -check-prefix=NOT-R2-R6 -check-prefix=GP64
13; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \
14; RUN:    -check-prefix=ALL -check-prefix=NOT-R2-R6 -check-prefix=GP64
15; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \
16; RUN:    -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP64
17; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \
18; RUN:    -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP64
19
20define signext i1 @sub_i1(i1 signext %a, i1 signext %b) {
21entry:
22; ALL-LABEL: sub_i1:
23
24  ; ALL:            subu    $[[T0:[0-9]+]], $4, $5
25  ; ALL:            sll     $[[T0]], $[[T0]], 31
26  ; ALL:            sra     $2, $[[T0]], 31
27
28  %r = sub i1 %a, %b
29  ret i1 %r
30}
31
32define signext i8 @sub_i8(i8 signext %a, i8 signext %b) {
33entry:
34; ALL-LABEL: sub_i8:
35
36  ; NOT-R2-R6:      subu    $[[T0:[0-9]+]], $4, $5
37  ; NOT-R2-R6:      sll     $[[T0]], $[[T0]], 24
38  ; NOT-R2-R6:      sra     $2, $[[T0]], 24
39
40  ; R2-R6:          subu    $[[T0:[0-9]+]], $4, $5
41  ; R2-R6:          seb     $2, $[[T0:[0-9]+]]
42
43  %r = sub i8 %a, %b
44  ret i8 %r
45}
46
47define signext i16 @sub_i16(i16 signext %a, i16 signext %b) {
48entry:
49; ALL-LABEL: sub_i16:
50
51  ; NOT-R2-R6:      subu    $[[T0:[0-9]+]], $4, $5
52  ; NOT-R2-R6:      sll     $[[T0]], $[[T0]], 16
53  ; NOT-R2-R6:      sra     $2, $[[T0]], 16
54
55  ; R2-R6:          subu    $[[T0:[0-9]+]], $4, $5
56  ; R2-R6:          seh     $2, $[[T0:[0-9]+]]
57
58  %r = sub i16 %a, %b
59  ret i16 %r
60}
61
62define signext i32 @sub_i32(i32 signext %a, i32 signext %b) {
63entry:
64; ALL-LABEL: sub_i32:
65
66  ; ALL:            subu    $2, $4, $5
67
68  %r = sub i32 %a, %b
69  ret i32 %r
70}
71
72define signext i64 @sub_i64(i64 signext %a, i64 signext %b) {
73entry:
74; ALL-LABEL: sub_i64:
75
76  ; GP32:           subu    $3, $5, $7
77  ; GP32:           sltu    $[[T0:[0-9]+]], $5, $7
78  ; GP32:           addu    $[[T1:[0-9]+]], $[[T0]], $6
79  ; GP32:           subu    $2, $4, $[[T1]]
80
81  ; GP64:           dsubu   $2, $4, $5
82
83  %r = sub i64 %a, %b
84  ret i64 %r
85}
86
87define signext i128 @sub_i128(i128 signext %a, i128 signext %b) {
88entry:
89; ALL-LABEL: sub_i128:
90
91  ; GP32:       lw        $[[T0:[0-9]+]], 20($sp)
92  ; GP32:       sltu      $[[T1:[0-9]+]], $5, $[[T0]]
93  ; GP32:       lw        $[[T2:[0-9]+]], 16($sp)
94  ; GP32:       addu      $[[T3:[0-9]+]], $[[T1]], $[[T2]]
95  ; GP32:       lw        $[[T4:[0-9]+]], 24($sp)
96  ; GP32:       lw        $[[T5:[0-9]+]], 28($sp)
97  ; GP32:       subu      $[[T6:[0-9]+]], $7, $[[T5]]
98  ; GP32:       subu      $2, $4, $[[T3]]
99  ; GP32:       sltu      $[[T8:[0-9]+]], $6, $[[T4]]
100  ; GP32:       addu      $[[T9:[0-9]+]], $[[T8]], $[[T0]]
101  ; GP32:       subu      $3, $5, $[[T9]]
102  ; GP32:       sltu      $[[T10:[0-9]+]], $7, $[[T5]]
103  ; GP32:       addu      $[[T11:[0-9]+]], $[[T10]], $[[T4]]
104  ; GP32:       subu      $4, $6, $[[T11]]
105  ; GP32:       move      $5, $[[T6]]
106
107  ; GP64:       dsubu     $3, $5, $7
108  ; GP64:       sltu      $[[T0:[0-9]+]], $5, $7
109  ; GP64:       daddu     $[[T1:[0-9]+]], $[[T0]], $6
110  ; GP64:       dsubu     $2, $4, $[[T1]]
111
112  %r = sub i128 %a, %b
113  ret i128 %r
114}
115