1; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \
2; RUN:    -check-prefix=NOT-R6 -check-prefix=GP32
3; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \
4; RUN:    -check-prefix=NOT-R6 -check-prefix=GP32
5; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \
6; RUN:    -check-prefix=NOT-R6 -check-prefix=GP32
7; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \
8; RUN:    -check-prefix=R6 -check-prefix=GP32
9; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \
10; RUN:    -check-prefix=NOT-R6 -check-prefix=GP64-NOT-R6
11; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \
12; RUN:    -check-prefix=NOT-R6 -check-prefix=GP64-NOT-R6
13; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \
14; RUN:    -check-prefix=NOT-R6 -check-prefix=GP64-NOT-R6
15; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \
16; RUN:    -check-prefix=NOT-R6 -check-prefix=GP64-NOT-R6
17; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \
18; RUN:    -check-prefix=R6 -check-prefix=64R6
19
20define zeroext i1 @udiv_i1(i1 zeroext %a, i1 zeroext %b) {
21entry:
22; ALL-LABEL: udiv_i1:
23
24  ; NOT-R6:       divu    $zero, $4, $5
25  ; NOT-R6:       teq     $5, $zero, 7
26  ; NOT-R6:       mflo    $2
27
28  ; R6:           divu    $2, $4, $5
29  ; R6:           teq     $5, $zero, 7
30
31  %r = udiv i1 %a, %b
32  ret i1 %r
33}
34
35define zeroext i8 @udiv_i8(i8 zeroext %a, i8 zeroext %b) {
36entry:
37; ALL-LABEL: udiv_i8:
38
39  ; NOT-R6:       divu    $zero, $4, $5
40  ; NOT-R6:       teq     $5, $zero, 7
41  ; NOT-R6:       mflo    $2
42
43  ; R6:           divu    $2, $4, $5
44  ; R6:           teq     $5, $zero, 7
45
46  %r = udiv i8 %a, %b
47  ret i8 %r
48}
49
50define zeroext i16 @udiv_i16(i16 zeroext %a, i16 zeroext %b) {
51entry:
52; ALL-LABEL: udiv_i16:
53
54  ; NOT-R6:       divu    $zero, $4, $5
55  ; NOT-R6:       teq     $5, $zero, 7
56  ; NOT-R6:       mflo    $2
57
58  ; R6:           divu    $2, $4, $5
59  ; R6:           teq     $5, $zero, 7
60
61  %r = udiv i16 %a, %b
62  ret i16 %r
63}
64
65define signext i32 @udiv_i32(i32 signext %a, i32 signext %b) {
66entry:
67; ALL-LABEL: udiv_i32:
68
69  ; NOT-R6:       divu    $zero, $4, $5
70  ; NOT-R6:       teq     $5, $zero, 7
71  ; NOT-R6:       mflo    $2
72
73  ; R6:           divu    $2, $4, $5
74  ; R6:           teq     $5, $zero, 7
75
76  %r = udiv i32 %a, %b
77  ret i32 %r
78}
79
80define signext i64 @udiv_i64(i64 signext %a, i64 signext %b) {
81entry:
82; ALL-LABEL: udiv_i64:
83
84  ; GP32:         lw      $25, %call16(__udivdi3)($gp)
85
86  ; GP64-NOT-R6:  ddivu   $zero, $4, $5
87  ; GP64-NOT-R6:  teq     $5, $zero, 7
88  ; GP64-NOT-R6:  mflo    $2
89
90  ; 64R6:         ddivu   $2, $4, $5
91  ; 64R6:         teq     $5, $zero, 7
92
93  %r = udiv i64 %a, %b
94  ret i64 %r
95}
96
97define signext i128 @udiv_i128(i128 signext %a, i128 signext %b) {
98entry:
99; ALL-LABEL: udiv_i128:
100
101  ; GP32:         lw      $25, %call16(__udivti3)($gp)
102
103  ; GP64-NOT-R6:  ld      $25, %call16(__udivti3)($gp)
104  ; 64-R6:        ld      $25, %call16(__udivti3)($gp)
105
106  %r = udiv i128 %a, %b
107  ret i128 %r
108}
109