1; Test the MSA intrinsics that are encoded with the 2R instruction format and
2; convert scalars to vectors.
3
4; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | \
5; RUN:   FileCheck %s -check-prefix=MIPS-ANY -check-prefix=MIPS32
6; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | \
7; RUN:   FileCheck %s -check-prefix=MIPS-ANY -check-prefix=MIPS32
8; RUN: llc -march=mips64 -mcpu=mips64r2 -mattr=+msa,+fp64 < %s | \
9; RUN:   FileCheck %s -check-prefix=MIPS-ANY -check-prefix=MIPS64
10; RUN: llc -march=mips64el -mcpu=mips64r2 -mattr=+msa,+fp64 < %s | \
11; RUN:   FileCheck %s -check-prefix=MIPS-ANY -check-prefix=MIPS64
12
13@llvm_mips_fill_b_ARG1 = global i32 23, align 16
14@llvm_mips_fill_b_RES  = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
15
16define void @llvm_mips_fill_b_test() nounwind {
17entry:
18  %0 = load i32* @llvm_mips_fill_b_ARG1
19  %1 = tail call <16 x i8> @llvm.mips.fill.b(i32 %0)
20  store <16 x i8> %1, <16 x i8>* @llvm_mips_fill_b_RES
21  ret void
22}
23
24declare <16 x i8> @llvm.mips.fill.b(i32) nounwind
25
26; MIPS-ANY: llvm_mips_fill_b_test:
27; MIPS32-DAG: lw [[R1:\$[0-9]+]],
28; MIPS64-DAG: ld [[R1:\$[0-9]+]],
29; MIPS-ANY-DAG: fill.b [[R2:\$w[0-9]+]], [[R1]]
30; MIPS-ANY-DAG: st.b [[R2]],
31; MIPS-ANY: .size llvm_mips_fill_b_test
32;
33@llvm_mips_fill_h_ARG1 = global i32 23, align 16
34@llvm_mips_fill_h_RES  = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16
35
36define void @llvm_mips_fill_h_test() nounwind {
37entry:
38  %0 = load i32* @llvm_mips_fill_h_ARG1
39  %1 = tail call <8 x i16> @llvm.mips.fill.h(i32 %0)
40  store <8 x i16> %1, <8 x i16>* @llvm_mips_fill_h_RES
41  ret void
42}
43
44declare <8 x i16> @llvm.mips.fill.h(i32) nounwind
45
46; MIPS-ANY: llvm_mips_fill_h_test:
47; MIPS32-DAG: lw [[R1:\$[0-9]+]],
48; MIPS64-DAG: ld [[R1:\$[0-9]+]],
49; MIPS-ANY-DAG: fill.h [[R2:\$w[0-9]+]], [[R1]]
50; MIPS-ANY-DAG: st.h [[R2]],
51; MIPS-ANY: .size llvm_mips_fill_h_test
52;
53@llvm_mips_fill_w_ARG1 = global i32 23, align 16
54@llvm_mips_fill_w_RES  = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
55
56define void @llvm_mips_fill_w_test() nounwind {
57entry:
58  %0 = load i32* @llvm_mips_fill_w_ARG1
59  %1 = tail call <4 x i32> @llvm.mips.fill.w(i32 %0)
60  store <4 x i32> %1, <4 x i32>* @llvm_mips_fill_w_RES
61  ret void
62}
63
64declare <4 x i32> @llvm.mips.fill.w(i32) nounwind
65
66; MIPS-ANY: llvm_mips_fill_w_test:
67; MIPS32-DAG: lw [[R1:\$[0-9]+]],
68; MIPS64-DAG: ld [[R1:\$[0-9]+]],
69; MIPS-ANY-DAG: fill.w [[R2:\$w[0-9]+]], [[R1]]
70; MIPS-ANY-DAG: st.w [[R2]],
71; MIPS-ANY: .size llvm_mips_fill_w_test
72;
73@llvm_mips_fill_d_ARG1 = global i64 23, align 16
74@llvm_mips_fill_d_RES  = global <2 x i64> <i64 0, i64 0>, align 16
75
76define void @llvm_mips_fill_d_test() nounwind {
77entry:
78  %0 = load i64* @llvm_mips_fill_d_ARG1
79  %1 = tail call <2 x i64> @llvm.mips.fill.d(i64 %0)
80  store <2 x i64> %1, <2 x i64>* @llvm_mips_fill_d_RES
81  ret void
82}
83
84declare <2 x i64> @llvm.mips.fill.d(i64) nounwind
85
86; MIPS-ANY: llvm_mips_fill_d_test:
87; MIPS32-DAG: lw [[R1:\$[0-9]+]], 0(
88; MIPS32-DAG: lw [[R2:\$[0-9]+]], 4(
89; MIPS64-DAG: ld [[R1:\$[0-9]+]], %got_disp(llvm_mips_fill_d_ARG1)
90; MIPS32-DAG: ldi.b [[R3:\$w[0-9]+]], 0
91; MIPS32-DAG: insert.w [[R3]][0], [[R1]]
92; MIPS32-DAG: insert.w [[R3]][1], [[R2]]
93; MIPS32-DAG: insert.w [[R3]][2], [[R1]]
94; MIPS32-DAG: insert.w [[R3]][3], [[R2]]
95; MIPS64-DAG: fill.d [[WD:\$w[0-9]+]], [[R1]]
96; MIPS32-DAG: st.w [[R3]],
97; MIPS64-DAG: ld [[RD:\$[0-9]+]], %got_disp(llvm_mips_fill_d_RES)
98; MIPS64-DAG: st.d [[WD]], 0([[RD]])
99; MIPS-ANY: .size llvm_mips_fill_d_test
100;