1; Test the MSA intrinsics that are encoded with the 2R instruction format and
2; convert scalars to vectors.
3
4; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
5; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s
6
7@llvm_mips_fill_b_ARG1 = global i32 23, align 16
8@llvm_mips_fill_b_RES  = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
9
10define void @llvm_mips_fill_b_test() nounwind {
11entry:
12  %0 = load i32* @llvm_mips_fill_b_ARG1
13  %1 = tail call <16 x i8> @llvm.mips.fill.b(i32 %0)
14  store <16 x i8> %1, <16 x i8>* @llvm_mips_fill_b_RES
15  ret void
16}
17
18declare <16 x i8> @llvm.mips.fill.b(i32) nounwind
19
20; CHECK: llvm_mips_fill_b_test:
21; CHECK-DAG: lw [[R1:\$[0-9]+]],
22; CHECK-DAG: fill.b [[R2:\$w[0-9]+]], [[R1]]
23; CHECK-DAG: st.b [[R2]],
24; CHECK: .size llvm_mips_fill_b_test
25;
26@llvm_mips_fill_h_ARG1 = global i32 23, align 16
27@llvm_mips_fill_h_RES  = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16
28
29define void @llvm_mips_fill_h_test() nounwind {
30entry:
31  %0 = load i32* @llvm_mips_fill_h_ARG1
32  %1 = tail call <8 x i16> @llvm.mips.fill.h(i32 %0)
33  store <8 x i16> %1, <8 x i16>* @llvm_mips_fill_h_RES
34  ret void
35}
36
37declare <8 x i16> @llvm.mips.fill.h(i32) nounwind
38
39; CHECK: llvm_mips_fill_h_test:
40; CHECK-DAG: lw [[R1:\$[0-9]+]],
41; CHECK-DAG: fill.h [[R2:\$w[0-9]+]], [[R1]]
42; CHECK-DAG: st.h [[R2]],
43; CHECK: .size llvm_mips_fill_h_test
44;
45@llvm_mips_fill_w_ARG1 = global i32 23, align 16
46@llvm_mips_fill_w_RES  = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
47
48define void @llvm_mips_fill_w_test() nounwind {
49entry:
50  %0 = load i32* @llvm_mips_fill_w_ARG1
51  %1 = tail call <4 x i32> @llvm.mips.fill.w(i32 %0)
52  store <4 x i32> %1, <4 x i32>* @llvm_mips_fill_w_RES
53  ret void
54}
55
56declare <4 x i32> @llvm.mips.fill.w(i32) nounwind
57
58; CHECK: llvm_mips_fill_w_test:
59; CHECK-DAG: lw [[R1:\$[0-9]+]],
60; CHECK-DAG: fill.w [[R2:\$w[0-9]+]], [[R1]]
61; CHECK-DAG: st.w [[R2]],
62; CHECK: .size llvm_mips_fill_w_test
63;
64@llvm_mips_fill_d_ARG1 = global i64 23, align 16
65@llvm_mips_fill_d_RES  = global <2 x i64> <i64 0, i64 0>, align 16
66
67define void @llvm_mips_fill_d_test() nounwind {
68entry:
69  %0 = load i64* @llvm_mips_fill_d_ARG1
70  %1 = tail call <2 x i64> @llvm.mips.fill.d(i64 %0)
71  store <2 x i64> %1, <2 x i64>* @llvm_mips_fill_d_RES
72  ret void
73}
74
75declare <2 x i64> @llvm.mips.fill.d(i64) nounwind
76
77; CHECK: llvm_mips_fill_d_test:
78; CHECK-DAG: lw [[R1:\$[0-9]+]], 0(
79; CHECK-DAG: lw [[R2:\$[0-9]+]], 4(
80; CHECK-DAG: ldi.b [[R3:\$w[0-9]+]], 0
81; CHECK-DAG: insert.w [[R3]][0], [[R1]]
82; CHECK-DAG: insert.w [[R3]][1], [[R2]]
83; CHECK-DAG: insert.w [[R3]][2], [[R1]]
84; CHECK-DAG: insert.w [[R3]][3], [[R2]]
85; CHECK-DAG: st.w [[R3]],
86; CHECK: .size llvm_mips_fill_d_test
87;
88