1; Test the MSA intrinsics that are encoded with the 3R instruction format. 2; There are lots of these so this covers those beginning with 'm' 3 4; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s 5; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s 6 7@llvm_mips_max_a_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 8@llvm_mips_max_a_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16 9@llvm_mips_max_a_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16 10 11define void @llvm_mips_max_a_b_test() nounwind { 12entry: 13 %0 = load <16 x i8>* @llvm_mips_max_a_b_ARG1 14 %1 = load <16 x i8>* @llvm_mips_max_a_b_ARG2 15 %2 = tail call <16 x i8> @llvm.mips.max.a.b(<16 x i8> %0, <16 x i8> %1) 16 store <16 x i8> %2, <16 x i8>* @llvm_mips_max_a_b_RES 17 ret void 18} 19 20declare <16 x i8> @llvm.mips.max.a.b(<16 x i8>, <16 x i8>) nounwind 21 22; CHECK: llvm_mips_max_a_b_test: 23; CHECK: ld.b 24; CHECK: ld.b 25; CHECK: max_a.b 26; CHECK: st.b 27; CHECK: .size llvm_mips_max_a_b_test 28; 29@llvm_mips_max_a_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16 30@llvm_mips_max_a_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16 31@llvm_mips_max_a_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16 32 33define void @llvm_mips_max_a_h_test() nounwind { 34entry: 35 %0 = load <8 x i16>* @llvm_mips_max_a_h_ARG1 36 %1 = load <8 x i16>* @llvm_mips_max_a_h_ARG2 37 %2 = tail call <8 x i16> @llvm.mips.max.a.h(<8 x i16> %0, <8 x i16> %1) 38 store <8 x i16> %2, <8 x i16>* @llvm_mips_max_a_h_RES 39 ret void 40} 41 42declare <8 x i16> @llvm.mips.max.a.h(<8 x i16>, <8 x i16>) nounwind 43 44; CHECK: llvm_mips_max_a_h_test: 45; CHECK: ld.h 46; CHECK: ld.h 47; CHECK: max_a.h 48; CHECK: st.h 49; CHECK: .size llvm_mips_max_a_h_test 50; 51@llvm_mips_max_a_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16 52@llvm_mips_max_a_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16 53@llvm_mips_max_a_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16 54 55define void @llvm_mips_max_a_w_test() nounwind { 56entry: 57 %0 = load <4 x i32>* @llvm_mips_max_a_w_ARG1 58 %1 = load <4 x i32>* @llvm_mips_max_a_w_ARG2 59 %2 = tail call <4 x i32> @llvm.mips.max.a.w(<4 x i32> %0, <4 x i32> %1) 60 store <4 x i32> %2, <4 x i32>* @llvm_mips_max_a_w_RES 61 ret void 62} 63 64declare <4 x i32> @llvm.mips.max.a.w(<4 x i32>, <4 x i32>) nounwind 65 66; CHECK: llvm_mips_max_a_w_test: 67; CHECK: ld.w 68; CHECK: ld.w 69; CHECK: max_a.w 70; CHECK: st.w 71; CHECK: .size llvm_mips_max_a_w_test 72; 73@llvm_mips_max_a_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16 74@llvm_mips_max_a_d_ARG2 = global <2 x i64> <i64 2, i64 3>, align 16 75@llvm_mips_max_a_d_RES = global <2 x i64> <i64 0, i64 0>, align 16 76 77define void @llvm_mips_max_a_d_test() nounwind { 78entry: 79 %0 = load <2 x i64>* @llvm_mips_max_a_d_ARG1 80 %1 = load <2 x i64>* @llvm_mips_max_a_d_ARG2 81 %2 = tail call <2 x i64> @llvm.mips.max.a.d(<2 x i64> %0, <2 x i64> %1) 82 store <2 x i64> %2, <2 x i64>* @llvm_mips_max_a_d_RES 83 ret void 84} 85 86declare <2 x i64> @llvm.mips.max.a.d(<2 x i64>, <2 x i64>) nounwind 87 88; CHECK: llvm_mips_max_a_d_test: 89; CHECK: ld.d 90; CHECK: ld.d 91; CHECK: max_a.d 92; CHECK: st.d 93; CHECK: .size llvm_mips_max_a_d_test 94; 95@llvm_mips_max_s_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 96@llvm_mips_max_s_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16 97@llvm_mips_max_s_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16 98 99define void @llvm_mips_max_s_b_test() nounwind { 100entry: 101 %0 = load <16 x i8>* @llvm_mips_max_s_b_ARG1 102 %1 = load <16 x i8>* @llvm_mips_max_s_b_ARG2 103 %2 = tail call <16 x i8> @llvm.mips.max.s.b(<16 x i8> %0, <16 x i8> %1) 104 store <16 x i8> %2, <16 x i8>* @llvm_mips_max_s_b_RES 105 ret void 106} 107 108declare <16 x i8> @llvm.mips.max.s.b(<16 x i8>, <16 x i8>) nounwind 109 110; CHECK: llvm_mips_max_s_b_test: 111; CHECK: ld.b 112; CHECK: ld.b 113; CHECK: max_s.b 114; CHECK: st.b 115; CHECK: .size llvm_mips_max_s_b_test 116; 117@llvm_mips_max_s_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16 118@llvm_mips_max_s_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16 119@llvm_mips_max_s_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16 120 121define void @llvm_mips_max_s_h_test() nounwind { 122entry: 123 %0 = load <8 x i16>* @llvm_mips_max_s_h_ARG1 124 %1 = load <8 x i16>* @llvm_mips_max_s_h_ARG2 125 %2 = tail call <8 x i16> @llvm.mips.max.s.h(<8 x i16> %0, <8 x i16> %1) 126 store <8 x i16> %2, <8 x i16>* @llvm_mips_max_s_h_RES 127 ret void 128} 129 130declare <8 x i16> @llvm.mips.max.s.h(<8 x i16>, <8 x i16>) nounwind 131 132; CHECK: llvm_mips_max_s_h_test: 133; CHECK: ld.h 134; CHECK: ld.h 135; CHECK: max_s.h 136; CHECK: st.h 137; CHECK: .size llvm_mips_max_s_h_test 138; 139@llvm_mips_max_s_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16 140@llvm_mips_max_s_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16 141@llvm_mips_max_s_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16 142 143define void @llvm_mips_max_s_w_test() nounwind { 144entry: 145 %0 = load <4 x i32>* @llvm_mips_max_s_w_ARG1 146 %1 = load <4 x i32>* @llvm_mips_max_s_w_ARG2 147 %2 = tail call <4 x i32> @llvm.mips.max.s.w(<4 x i32> %0, <4 x i32> %1) 148 store <4 x i32> %2, <4 x i32>* @llvm_mips_max_s_w_RES 149 ret void 150} 151 152declare <4 x i32> @llvm.mips.max.s.w(<4 x i32>, <4 x i32>) nounwind 153 154; CHECK: llvm_mips_max_s_w_test: 155; CHECK: ld.w 156; CHECK: ld.w 157; CHECK: max_s.w 158; CHECK: st.w 159; CHECK: .size llvm_mips_max_s_w_test 160; 161@llvm_mips_max_s_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16 162@llvm_mips_max_s_d_ARG2 = global <2 x i64> <i64 2, i64 3>, align 16 163@llvm_mips_max_s_d_RES = global <2 x i64> <i64 0, i64 0>, align 16 164 165define void @llvm_mips_max_s_d_test() nounwind { 166entry: 167 %0 = load <2 x i64>* @llvm_mips_max_s_d_ARG1 168 %1 = load <2 x i64>* @llvm_mips_max_s_d_ARG2 169 %2 = tail call <2 x i64> @llvm.mips.max.s.d(<2 x i64> %0, <2 x i64> %1) 170 store <2 x i64> %2, <2 x i64>* @llvm_mips_max_s_d_RES 171 ret void 172} 173 174declare <2 x i64> @llvm.mips.max.s.d(<2 x i64>, <2 x i64>) nounwind 175 176; CHECK: llvm_mips_max_s_d_test: 177; CHECK: ld.d 178; CHECK: ld.d 179; CHECK: max_s.d 180; CHECK: st.d 181; CHECK: .size llvm_mips_max_s_d_test 182; 183@llvm_mips_max_u_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 184@llvm_mips_max_u_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16 185@llvm_mips_max_u_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16 186 187define void @llvm_mips_max_u_b_test() nounwind { 188entry: 189 %0 = load <16 x i8>* @llvm_mips_max_u_b_ARG1 190 %1 = load <16 x i8>* @llvm_mips_max_u_b_ARG2 191 %2 = tail call <16 x i8> @llvm.mips.max.u.b(<16 x i8> %0, <16 x i8> %1) 192 store <16 x i8> %2, <16 x i8>* @llvm_mips_max_u_b_RES 193 ret void 194} 195 196declare <16 x i8> @llvm.mips.max.u.b(<16 x i8>, <16 x i8>) nounwind 197 198; CHECK: llvm_mips_max_u_b_test: 199; CHECK: ld.b 200; CHECK: ld.b 201; CHECK: max_u.b 202; CHECK: st.b 203; CHECK: .size llvm_mips_max_u_b_test 204; 205@llvm_mips_max_u_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16 206@llvm_mips_max_u_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16 207@llvm_mips_max_u_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16 208 209define void @llvm_mips_max_u_h_test() nounwind { 210entry: 211 %0 = load <8 x i16>* @llvm_mips_max_u_h_ARG1 212 %1 = load <8 x i16>* @llvm_mips_max_u_h_ARG2 213 %2 = tail call <8 x i16> @llvm.mips.max.u.h(<8 x i16> %0, <8 x i16> %1) 214 store <8 x i16> %2, <8 x i16>* @llvm_mips_max_u_h_RES 215 ret void 216} 217 218declare <8 x i16> @llvm.mips.max.u.h(<8 x i16>, <8 x i16>) nounwind 219 220; CHECK: llvm_mips_max_u_h_test: 221; CHECK: ld.h 222; CHECK: ld.h 223; CHECK: max_u.h 224; CHECK: st.h 225; CHECK: .size llvm_mips_max_u_h_test 226; 227@llvm_mips_max_u_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16 228@llvm_mips_max_u_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16 229@llvm_mips_max_u_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16 230 231define void @llvm_mips_max_u_w_test() nounwind { 232entry: 233 %0 = load <4 x i32>* @llvm_mips_max_u_w_ARG1 234 %1 = load <4 x i32>* @llvm_mips_max_u_w_ARG2 235 %2 = tail call <4 x i32> @llvm.mips.max.u.w(<4 x i32> %0, <4 x i32> %1) 236 store <4 x i32> %2, <4 x i32>* @llvm_mips_max_u_w_RES 237 ret void 238} 239 240declare <4 x i32> @llvm.mips.max.u.w(<4 x i32>, <4 x i32>) nounwind 241 242; CHECK: llvm_mips_max_u_w_test: 243; CHECK: ld.w 244; CHECK: ld.w 245; CHECK: max_u.w 246; CHECK: st.w 247; CHECK: .size llvm_mips_max_u_w_test 248; 249@llvm_mips_max_u_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16 250@llvm_mips_max_u_d_ARG2 = global <2 x i64> <i64 2, i64 3>, align 16 251@llvm_mips_max_u_d_RES = global <2 x i64> <i64 0, i64 0>, align 16 252 253define void @llvm_mips_max_u_d_test() nounwind { 254entry: 255 %0 = load <2 x i64>* @llvm_mips_max_u_d_ARG1 256 %1 = load <2 x i64>* @llvm_mips_max_u_d_ARG2 257 %2 = tail call <2 x i64> @llvm.mips.max.u.d(<2 x i64> %0, <2 x i64> %1) 258 store <2 x i64> %2, <2 x i64>* @llvm_mips_max_u_d_RES 259 ret void 260} 261 262declare <2 x i64> @llvm.mips.max.u.d(<2 x i64>, <2 x i64>) nounwind 263 264; CHECK: llvm_mips_max_u_d_test: 265; CHECK: ld.d 266; CHECK: ld.d 267; CHECK: max_u.d 268; CHECK: st.d 269; CHECK: .size llvm_mips_max_u_d_test 270; 271@llvm_mips_min_a_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 272@llvm_mips_min_a_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16 273@llvm_mips_min_a_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16 274 275define void @llvm_mips_min_a_b_test() nounwind { 276entry: 277 %0 = load <16 x i8>* @llvm_mips_min_a_b_ARG1 278 %1 = load <16 x i8>* @llvm_mips_min_a_b_ARG2 279 %2 = tail call <16 x i8> @llvm.mips.min.a.b(<16 x i8> %0, <16 x i8> %1) 280 store <16 x i8> %2, <16 x i8>* @llvm_mips_min_a_b_RES 281 ret void 282} 283 284declare <16 x i8> @llvm.mips.min.a.b(<16 x i8>, <16 x i8>) nounwind 285 286; CHECK: llvm_mips_min_a_b_test: 287; CHECK: ld.b 288; CHECK: ld.b 289; CHECK: min_a.b 290; CHECK: st.b 291; CHECK: .size llvm_mips_min_a_b_test 292; 293@llvm_mips_min_a_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16 294@llvm_mips_min_a_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16 295@llvm_mips_min_a_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16 296 297define void @llvm_mips_min_a_h_test() nounwind { 298entry: 299 %0 = load <8 x i16>* @llvm_mips_min_a_h_ARG1 300 %1 = load <8 x i16>* @llvm_mips_min_a_h_ARG2 301 %2 = tail call <8 x i16> @llvm.mips.min.a.h(<8 x i16> %0, <8 x i16> %1) 302 store <8 x i16> %2, <8 x i16>* @llvm_mips_min_a_h_RES 303 ret void 304} 305 306declare <8 x i16> @llvm.mips.min.a.h(<8 x i16>, <8 x i16>) nounwind 307 308; CHECK: llvm_mips_min_a_h_test: 309; CHECK: ld.h 310; CHECK: ld.h 311; CHECK: min_a.h 312; CHECK: st.h 313; CHECK: .size llvm_mips_min_a_h_test 314; 315@llvm_mips_min_a_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16 316@llvm_mips_min_a_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16 317@llvm_mips_min_a_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16 318 319define void @llvm_mips_min_a_w_test() nounwind { 320entry: 321 %0 = load <4 x i32>* @llvm_mips_min_a_w_ARG1 322 %1 = load <4 x i32>* @llvm_mips_min_a_w_ARG2 323 %2 = tail call <4 x i32> @llvm.mips.min.a.w(<4 x i32> %0, <4 x i32> %1) 324 store <4 x i32> %2, <4 x i32>* @llvm_mips_min_a_w_RES 325 ret void 326} 327 328declare <4 x i32> @llvm.mips.min.a.w(<4 x i32>, <4 x i32>) nounwind 329 330; CHECK: llvm_mips_min_a_w_test: 331; CHECK: ld.w 332; CHECK: ld.w 333; CHECK: min_a.w 334; CHECK: st.w 335; CHECK: .size llvm_mips_min_a_w_test 336; 337@llvm_mips_min_a_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16 338@llvm_mips_min_a_d_ARG2 = global <2 x i64> <i64 2, i64 3>, align 16 339@llvm_mips_min_a_d_RES = global <2 x i64> <i64 0, i64 0>, align 16 340 341define void @llvm_mips_min_a_d_test() nounwind { 342entry: 343 %0 = load <2 x i64>* @llvm_mips_min_a_d_ARG1 344 %1 = load <2 x i64>* @llvm_mips_min_a_d_ARG2 345 %2 = tail call <2 x i64> @llvm.mips.min.a.d(<2 x i64> %0, <2 x i64> %1) 346 store <2 x i64> %2, <2 x i64>* @llvm_mips_min_a_d_RES 347 ret void 348} 349 350declare <2 x i64> @llvm.mips.min.a.d(<2 x i64>, <2 x i64>) nounwind 351 352; CHECK: llvm_mips_min_a_d_test: 353; CHECK: ld.d 354; CHECK: ld.d 355; CHECK: min_a.d 356; CHECK: st.d 357; CHECK: .size llvm_mips_min_a_d_test 358; 359@llvm_mips_min_s_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 360@llvm_mips_min_s_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16 361@llvm_mips_min_s_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16 362 363define void @llvm_mips_min_s_b_test() nounwind { 364entry: 365 %0 = load <16 x i8>* @llvm_mips_min_s_b_ARG1 366 %1 = load <16 x i8>* @llvm_mips_min_s_b_ARG2 367 %2 = tail call <16 x i8> @llvm.mips.min.s.b(<16 x i8> %0, <16 x i8> %1) 368 store <16 x i8> %2, <16 x i8>* @llvm_mips_min_s_b_RES 369 ret void 370} 371 372declare <16 x i8> @llvm.mips.min.s.b(<16 x i8>, <16 x i8>) nounwind 373 374; CHECK: llvm_mips_min_s_b_test: 375; CHECK: ld.b 376; CHECK: ld.b 377; CHECK: min_s.b 378; CHECK: st.b 379; CHECK: .size llvm_mips_min_s_b_test 380; 381@llvm_mips_min_s_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16 382@llvm_mips_min_s_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16 383@llvm_mips_min_s_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16 384 385define void @llvm_mips_min_s_h_test() nounwind { 386entry: 387 %0 = load <8 x i16>* @llvm_mips_min_s_h_ARG1 388 %1 = load <8 x i16>* @llvm_mips_min_s_h_ARG2 389 %2 = tail call <8 x i16> @llvm.mips.min.s.h(<8 x i16> %0, <8 x i16> %1) 390 store <8 x i16> %2, <8 x i16>* @llvm_mips_min_s_h_RES 391 ret void 392} 393 394declare <8 x i16> @llvm.mips.min.s.h(<8 x i16>, <8 x i16>) nounwind 395 396; CHECK: llvm_mips_min_s_h_test: 397; CHECK: ld.h 398; CHECK: ld.h 399; CHECK: min_s.h 400; CHECK: st.h 401; CHECK: .size llvm_mips_min_s_h_test 402; 403@llvm_mips_min_s_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16 404@llvm_mips_min_s_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16 405@llvm_mips_min_s_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16 406 407define void @llvm_mips_min_s_w_test() nounwind { 408entry: 409 %0 = load <4 x i32>* @llvm_mips_min_s_w_ARG1 410 %1 = load <4 x i32>* @llvm_mips_min_s_w_ARG2 411 %2 = tail call <4 x i32> @llvm.mips.min.s.w(<4 x i32> %0, <4 x i32> %1) 412 store <4 x i32> %2, <4 x i32>* @llvm_mips_min_s_w_RES 413 ret void 414} 415 416declare <4 x i32> @llvm.mips.min.s.w(<4 x i32>, <4 x i32>) nounwind 417 418; CHECK: llvm_mips_min_s_w_test: 419; CHECK: ld.w 420; CHECK: ld.w 421; CHECK: min_s.w 422; CHECK: st.w 423; CHECK: .size llvm_mips_min_s_w_test 424; 425@llvm_mips_min_s_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16 426@llvm_mips_min_s_d_ARG2 = global <2 x i64> <i64 2, i64 3>, align 16 427@llvm_mips_min_s_d_RES = global <2 x i64> <i64 0, i64 0>, align 16 428 429define void @llvm_mips_min_s_d_test() nounwind { 430entry: 431 %0 = load <2 x i64>* @llvm_mips_min_s_d_ARG1 432 %1 = load <2 x i64>* @llvm_mips_min_s_d_ARG2 433 %2 = tail call <2 x i64> @llvm.mips.min.s.d(<2 x i64> %0, <2 x i64> %1) 434 store <2 x i64> %2, <2 x i64>* @llvm_mips_min_s_d_RES 435 ret void 436} 437 438declare <2 x i64> @llvm.mips.min.s.d(<2 x i64>, <2 x i64>) nounwind 439 440; CHECK: llvm_mips_min_s_d_test: 441; CHECK: ld.d 442; CHECK: ld.d 443; CHECK: min_s.d 444; CHECK: st.d 445; CHECK: .size llvm_mips_min_s_d_test 446; 447@llvm_mips_min_u_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 448@llvm_mips_min_u_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16 449@llvm_mips_min_u_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16 450 451define void @llvm_mips_min_u_b_test() nounwind { 452entry: 453 %0 = load <16 x i8>* @llvm_mips_min_u_b_ARG1 454 %1 = load <16 x i8>* @llvm_mips_min_u_b_ARG2 455 %2 = tail call <16 x i8> @llvm.mips.min.u.b(<16 x i8> %0, <16 x i8> %1) 456 store <16 x i8> %2, <16 x i8>* @llvm_mips_min_u_b_RES 457 ret void 458} 459 460declare <16 x i8> @llvm.mips.min.u.b(<16 x i8>, <16 x i8>) nounwind 461 462; CHECK: llvm_mips_min_u_b_test: 463; CHECK: ld.b 464; CHECK: ld.b 465; CHECK: min_u.b 466; CHECK: st.b 467; CHECK: .size llvm_mips_min_u_b_test 468; 469@llvm_mips_min_u_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16 470@llvm_mips_min_u_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16 471@llvm_mips_min_u_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16 472 473define void @llvm_mips_min_u_h_test() nounwind { 474entry: 475 %0 = load <8 x i16>* @llvm_mips_min_u_h_ARG1 476 %1 = load <8 x i16>* @llvm_mips_min_u_h_ARG2 477 %2 = tail call <8 x i16> @llvm.mips.min.u.h(<8 x i16> %0, <8 x i16> %1) 478 store <8 x i16> %2, <8 x i16>* @llvm_mips_min_u_h_RES 479 ret void 480} 481 482declare <8 x i16> @llvm.mips.min.u.h(<8 x i16>, <8 x i16>) nounwind 483 484; CHECK: llvm_mips_min_u_h_test: 485; CHECK: ld.h 486; CHECK: ld.h 487; CHECK: min_u.h 488; CHECK: st.h 489; CHECK: .size llvm_mips_min_u_h_test 490; 491@llvm_mips_min_u_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16 492@llvm_mips_min_u_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16 493@llvm_mips_min_u_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16 494 495define void @llvm_mips_min_u_w_test() nounwind { 496entry: 497 %0 = load <4 x i32>* @llvm_mips_min_u_w_ARG1 498 %1 = load <4 x i32>* @llvm_mips_min_u_w_ARG2 499 %2 = tail call <4 x i32> @llvm.mips.min.u.w(<4 x i32> %0, <4 x i32> %1) 500 store <4 x i32> %2, <4 x i32>* @llvm_mips_min_u_w_RES 501 ret void 502} 503 504declare <4 x i32> @llvm.mips.min.u.w(<4 x i32>, <4 x i32>) nounwind 505 506; CHECK: llvm_mips_min_u_w_test: 507; CHECK: ld.w 508; CHECK: ld.w 509; CHECK: min_u.w 510; CHECK: st.w 511; CHECK: .size llvm_mips_min_u_w_test 512; 513@llvm_mips_min_u_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16 514@llvm_mips_min_u_d_ARG2 = global <2 x i64> <i64 2, i64 3>, align 16 515@llvm_mips_min_u_d_RES = global <2 x i64> <i64 0, i64 0>, align 16 516 517define void @llvm_mips_min_u_d_test() nounwind { 518entry: 519 %0 = load <2 x i64>* @llvm_mips_min_u_d_ARG1 520 %1 = load <2 x i64>* @llvm_mips_min_u_d_ARG2 521 %2 = tail call <2 x i64> @llvm.mips.min.u.d(<2 x i64> %0, <2 x i64> %1) 522 store <2 x i64> %2, <2 x i64>* @llvm_mips_min_u_d_RES 523 ret void 524} 525 526declare <2 x i64> @llvm.mips.min.u.d(<2 x i64>, <2 x i64>) nounwind 527 528; CHECK: llvm_mips_min_u_d_test: 529; CHECK: ld.d 530; CHECK: ld.d 531; CHECK: min_u.d 532; CHECK: st.d 533; CHECK: .size llvm_mips_min_u_d_test 534; 535@llvm_mips_mod_s_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 536@llvm_mips_mod_s_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16 537@llvm_mips_mod_s_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16 538 539define void @llvm_mips_mod_s_b_test() nounwind { 540entry: 541 %0 = load <16 x i8>* @llvm_mips_mod_s_b_ARG1 542 %1 = load <16 x i8>* @llvm_mips_mod_s_b_ARG2 543 %2 = tail call <16 x i8> @llvm.mips.mod.s.b(<16 x i8> %0, <16 x i8> %1) 544 store <16 x i8> %2, <16 x i8>* @llvm_mips_mod_s_b_RES 545 ret void 546} 547 548declare <16 x i8> @llvm.mips.mod.s.b(<16 x i8>, <16 x i8>) nounwind 549 550; CHECK: llvm_mips_mod_s_b_test: 551; CHECK: ld.b 552; CHECK: ld.b 553; CHECK: mod_s.b 554; CHECK: st.b 555; CHECK: .size llvm_mips_mod_s_b_test 556; 557@llvm_mips_mod_s_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16 558@llvm_mips_mod_s_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16 559@llvm_mips_mod_s_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16 560 561define void @llvm_mips_mod_s_h_test() nounwind { 562entry: 563 %0 = load <8 x i16>* @llvm_mips_mod_s_h_ARG1 564 %1 = load <8 x i16>* @llvm_mips_mod_s_h_ARG2 565 %2 = tail call <8 x i16> @llvm.mips.mod.s.h(<8 x i16> %0, <8 x i16> %1) 566 store <8 x i16> %2, <8 x i16>* @llvm_mips_mod_s_h_RES 567 ret void 568} 569 570declare <8 x i16> @llvm.mips.mod.s.h(<8 x i16>, <8 x i16>) nounwind 571 572; CHECK: llvm_mips_mod_s_h_test: 573; CHECK: ld.h 574; CHECK: ld.h 575; CHECK: mod_s.h 576; CHECK: st.h 577; CHECK: .size llvm_mips_mod_s_h_test 578; 579@llvm_mips_mod_s_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16 580@llvm_mips_mod_s_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16 581@llvm_mips_mod_s_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16 582 583define void @llvm_mips_mod_s_w_test() nounwind { 584entry: 585 %0 = load <4 x i32>* @llvm_mips_mod_s_w_ARG1 586 %1 = load <4 x i32>* @llvm_mips_mod_s_w_ARG2 587 %2 = tail call <4 x i32> @llvm.mips.mod.s.w(<4 x i32> %0, <4 x i32> %1) 588 store <4 x i32> %2, <4 x i32>* @llvm_mips_mod_s_w_RES 589 ret void 590} 591 592declare <4 x i32> @llvm.mips.mod.s.w(<4 x i32>, <4 x i32>) nounwind 593 594; CHECK: llvm_mips_mod_s_w_test: 595; CHECK: ld.w 596; CHECK: ld.w 597; CHECK: mod_s.w 598; CHECK: st.w 599; CHECK: .size llvm_mips_mod_s_w_test 600; 601@llvm_mips_mod_s_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16 602@llvm_mips_mod_s_d_ARG2 = global <2 x i64> <i64 2, i64 3>, align 16 603@llvm_mips_mod_s_d_RES = global <2 x i64> <i64 0, i64 0>, align 16 604 605define void @llvm_mips_mod_s_d_test() nounwind { 606entry: 607 %0 = load <2 x i64>* @llvm_mips_mod_s_d_ARG1 608 %1 = load <2 x i64>* @llvm_mips_mod_s_d_ARG2 609 %2 = tail call <2 x i64> @llvm.mips.mod.s.d(<2 x i64> %0, <2 x i64> %1) 610 store <2 x i64> %2, <2 x i64>* @llvm_mips_mod_s_d_RES 611 ret void 612} 613 614declare <2 x i64> @llvm.mips.mod.s.d(<2 x i64>, <2 x i64>) nounwind 615 616; CHECK: llvm_mips_mod_s_d_test: 617; CHECK: ld.d 618; CHECK: ld.d 619; CHECK: mod_s.d 620; CHECK: st.d 621; CHECK: .size llvm_mips_mod_s_d_test 622; 623@llvm_mips_mod_u_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 624@llvm_mips_mod_u_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16 625@llvm_mips_mod_u_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16 626 627define void @llvm_mips_mod_u_b_test() nounwind { 628entry: 629 %0 = load <16 x i8>* @llvm_mips_mod_u_b_ARG1 630 %1 = load <16 x i8>* @llvm_mips_mod_u_b_ARG2 631 %2 = tail call <16 x i8> @llvm.mips.mod.u.b(<16 x i8> %0, <16 x i8> %1) 632 store <16 x i8> %2, <16 x i8>* @llvm_mips_mod_u_b_RES 633 ret void 634} 635 636declare <16 x i8> @llvm.mips.mod.u.b(<16 x i8>, <16 x i8>) nounwind 637 638; CHECK: llvm_mips_mod_u_b_test: 639; CHECK: ld.b 640; CHECK: ld.b 641; CHECK: mod_u.b 642; CHECK: st.b 643; CHECK: .size llvm_mips_mod_u_b_test 644; 645@llvm_mips_mod_u_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16 646@llvm_mips_mod_u_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16 647@llvm_mips_mod_u_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16 648 649define void @llvm_mips_mod_u_h_test() nounwind { 650entry: 651 %0 = load <8 x i16>* @llvm_mips_mod_u_h_ARG1 652 %1 = load <8 x i16>* @llvm_mips_mod_u_h_ARG2 653 %2 = tail call <8 x i16> @llvm.mips.mod.u.h(<8 x i16> %0, <8 x i16> %1) 654 store <8 x i16> %2, <8 x i16>* @llvm_mips_mod_u_h_RES 655 ret void 656} 657 658declare <8 x i16> @llvm.mips.mod.u.h(<8 x i16>, <8 x i16>) nounwind 659 660; CHECK: llvm_mips_mod_u_h_test: 661; CHECK: ld.h 662; CHECK: ld.h 663; CHECK: mod_u.h 664; CHECK: st.h 665; CHECK: .size llvm_mips_mod_u_h_test 666; 667@llvm_mips_mod_u_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16 668@llvm_mips_mod_u_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16 669@llvm_mips_mod_u_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16 670 671define void @llvm_mips_mod_u_w_test() nounwind { 672entry: 673 %0 = load <4 x i32>* @llvm_mips_mod_u_w_ARG1 674 %1 = load <4 x i32>* @llvm_mips_mod_u_w_ARG2 675 %2 = tail call <4 x i32> @llvm.mips.mod.u.w(<4 x i32> %0, <4 x i32> %1) 676 store <4 x i32> %2, <4 x i32>* @llvm_mips_mod_u_w_RES 677 ret void 678} 679 680declare <4 x i32> @llvm.mips.mod.u.w(<4 x i32>, <4 x i32>) nounwind 681 682; CHECK: llvm_mips_mod_u_w_test: 683; CHECK: ld.w 684; CHECK: ld.w 685; CHECK: mod_u.w 686; CHECK: st.w 687; CHECK: .size llvm_mips_mod_u_w_test 688; 689@llvm_mips_mod_u_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16 690@llvm_mips_mod_u_d_ARG2 = global <2 x i64> <i64 2, i64 3>, align 16 691@llvm_mips_mod_u_d_RES = global <2 x i64> <i64 0, i64 0>, align 16 692 693define void @llvm_mips_mod_u_d_test() nounwind { 694entry: 695 %0 = load <2 x i64>* @llvm_mips_mod_u_d_ARG1 696 %1 = load <2 x i64>* @llvm_mips_mod_u_d_ARG2 697 %2 = tail call <2 x i64> @llvm.mips.mod.u.d(<2 x i64> %0, <2 x i64> %1) 698 store <2 x i64> %2, <2 x i64>* @llvm_mips_mod_u_d_RES 699 ret void 700} 701 702declare <2 x i64> @llvm.mips.mod.u.d(<2 x i64>, <2 x i64>) nounwind 703 704; CHECK: llvm_mips_mod_u_d_test: 705; CHECK: ld.d 706; CHECK: ld.d 707; CHECK: mod_u.d 708; CHECK: st.d 709; CHECK: .size llvm_mips_mod_u_d_test 710; 711@llvm_mips_mulv_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 712@llvm_mips_mulv_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16 713@llvm_mips_mulv_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16 714 715define void @llvm_mips_mulv_b_test() nounwind { 716entry: 717 %0 = load <16 x i8>* @llvm_mips_mulv_b_ARG1 718 %1 = load <16 x i8>* @llvm_mips_mulv_b_ARG2 719 %2 = tail call <16 x i8> @llvm.mips.mulv.b(<16 x i8> %0, <16 x i8> %1) 720 store <16 x i8> %2, <16 x i8>* @llvm_mips_mulv_b_RES 721 ret void 722} 723 724declare <16 x i8> @llvm.mips.mulv.b(<16 x i8>, <16 x i8>) nounwind 725 726; CHECK: llvm_mips_mulv_b_test: 727; CHECK: ld.b 728; CHECK: ld.b 729; CHECK: mulv.b 730; CHECK: st.b 731; CHECK: .size llvm_mips_mulv_b_test 732; 733@llvm_mips_mulv_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16 734@llvm_mips_mulv_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16 735@llvm_mips_mulv_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16 736 737define void @llvm_mips_mulv_h_test() nounwind { 738entry: 739 %0 = load <8 x i16>* @llvm_mips_mulv_h_ARG1 740 %1 = load <8 x i16>* @llvm_mips_mulv_h_ARG2 741 %2 = tail call <8 x i16> @llvm.mips.mulv.h(<8 x i16> %0, <8 x i16> %1) 742 store <8 x i16> %2, <8 x i16>* @llvm_mips_mulv_h_RES 743 ret void 744} 745 746declare <8 x i16> @llvm.mips.mulv.h(<8 x i16>, <8 x i16>) nounwind 747 748; CHECK: llvm_mips_mulv_h_test: 749; CHECK: ld.h 750; CHECK: ld.h 751; CHECK: mulv.h 752; CHECK: st.h 753; CHECK: .size llvm_mips_mulv_h_test 754; 755@llvm_mips_mulv_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16 756@llvm_mips_mulv_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16 757@llvm_mips_mulv_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16 758 759define void @llvm_mips_mulv_w_test() nounwind { 760entry: 761 %0 = load <4 x i32>* @llvm_mips_mulv_w_ARG1 762 %1 = load <4 x i32>* @llvm_mips_mulv_w_ARG2 763 %2 = tail call <4 x i32> @llvm.mips.mulv.w(<4 x i32> %0, <4 x i32> %1) 764 store <4 x i32> %2, <4 x i32>* @llvm_mips_mulv_w_RES 765 ret void 766} 767 768declare <4 x i32> @llvm.mips.mulv.w(<4 x i32>, <4 x i32>) nounwind 769 770; CHECK: llvm_mips_mulv_w_test: 771; CHECK: ld.w 772; CHECK: ld.w 773; CHECK: mulv.w 774; CHECK: st.w 775; CHECK: .size llvm_mips_mulv_w_test 776; 777@llvm_mips_mulv_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16 778@llvm_mips_mulv_d_ARG2 = global <2 x i64> <i64 2, i64 3>, align 16 779@llvm_mips_mulv_d_RES = global <2 x i64> <i64 0, i64 0>, align 16 780 781define void @llvm_mips_mulv_d_test() nounwind { 782entry: 783 %0 = load <2 x i64>* @llvm_mips_mulv_d_ARG1 784 %1 = load <2 x i64>* @llvm_mips_mulv_d_ARG2 785 %2 = tail call <2 x i64> @llvm.mips.mulv.d(<2 x i64> %0, <2 x i64> %1) 786 store <2 x i64> %2, <2 x i64>* @llvm_mips_mulv_d_RES 787 ret void 788} 789 790declare <2 x i64> @llvm.mips.mulv.d(<2 x i64>, <2 x i64>) nounwind 791 792; CHECK: llvm_mips_mulv_d_test: 793; CHECK: ld.d 794; CHECK: ld.d 795; CHECK: mulv.d 796; CHECK: st.d 797; CHECK: .size llvm_mips_mulv_d_test 798 799define void @mulv_b_test() nounwind { 800entry: 801 %0 = load <16 x i8>* @llvm_mips_mulv_b_ARG1 802 %1 = load <16 x i8>* @llvm_mips_mulv_b_ARG2 803 %2 = mul <16 x i8> %0, %1 804 store <16 x i8> %2, <16 x i8>* @llvm_mips_mulv_b_RES 805 ret void 806} 807 808; CHECK: mulv_b_test: 809; CHECK: ld.b 810; CHECK: ld.b 811; CHECK: mulv.b 812; CHECK: st.b 813; CHECK: .size mulv_b_test 814 815define void @mulv_h_test() nounwind { 816entry: 817 %0 = load <8 x i16>* @llvm_mips_mulv_h_ARG1 818 %1 = load <8 x i16>* @llvm_mips_mulv_h_ARG2 819 %2 = mul <8 x i16> %0, %1 820 store <8 x i16> %2, <8 x i16>* @llvm_mips_mulv_h_RES 821 ret void 822} 823 824; CHECK: mulv_h_test: 825; CHECK: ld.h 826; CHECK: ld.h 827; CHECK: mulv.h 828; CHECK: st.h 829; CHECK: .size mulv_h_test 830 831define void @mulv_w_test() nounwind { 832entry: 833 %0 = load <4 x i32>* @llvm_mips_mulv_w_ARG1 834 %1 = load <4 x i32>* @llvm_mips_mulv_w_ARG2 835 %2 = mul <4 x i32> %0, %1 836 store <4 x i32> %2, <4 x i32>* @llvm_mips_mulv_w_RES 837 ret void 838} 839 840; CHECK: mulv_w_test: 841; CHECK: ld.w 842; CHECK: ld.w 843; CHECK: mulv.w 844; CHECK: st.w 845; CHECK: .size mulv_w_test 846 847define void @mulv_d_test() nounwind { 848entry: 849 %0 = load <2 x i64>* @llvm_mips_mulv_d_ARG1 850 %1 = load <2 x i64>* @llvm_mips_mulv_d_ARG2 851 %2 = mul <2 x i64> %0, %1 852 store <2 x i64> %2, <2 x i64>* @llvm_mips_mulv_d_RES 853 ret void 854} 855 856; CHECK: mulv_d_test: 857; CHECK: ld.d 858; CHECK: ld.d 859; CHECK: mulv.d 860; CHECK: st.d 861; CHECK: .size mulv_d_test 862; 863