1; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s 2; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s 3 4declare <4 x float> @llvm.mips.fmax.w(<4 x float>, <4 x float>) nounwind 5declare <2 x double> @llvm.mips.fmax.d(<2 x double>, <2 x double>) nounwind 6declare <4 x float> @llvm.mips.fmin.w(<4 x float>, <4 x float>) nounwind 7declare <2 x double> @llvm.mips.fmin.d(<2 x double>, <2 x double>) nounwind 8 9define void @false_v4f32(<4 x i32>* %c, <4 x float>* %a, <4 x float>* %b) nounwind { 10 ; CHECK: false_v4f32: 11 12 %1 = load <4 x float>* %a 13 %2 = load <4 x float>* %b 14 %3 = fcmp false <4 x float> %1, %2 15 %4 = sext <4 x i1> %3 to <4 x i32> 16 store <4 x i32> %4, <4 x i32>* %c 17 ret void 18 19 ; (setcc $a, $b, SETFALSE) is always folded, so we won't get fcaf: 20 ; CHECK-DAG: ldi.b [[R1:\$w[0-9]+]], 0 21 ; CHECK-DAG: st.w [[R1]], 0($4) 22 ; CHECK: .size false_v4f32 23} 24 25define void @false_v2f64(<2 x i64>* %c, <2 x double>* %a, <2 x double>* %b) nounwind { 26 ; CHECK: false_v2f64: 27 28 %1 = load <2 x double>* %a 29 %2 = load <2 x double>* %b 30 %3 = fcmp false <2 x double> %1, %2 31 %4 = sext <2 x i1> %3 to <2 x i64> 32 store <2 x i64> %4, <2 x i64>* %c 33 ret void 34 35 ; (setcc $a, $b, SETFALSE) is always folded 36 ; CHECK-DAG: ldi.b [[R1:\$w[0-9]+]], 0 37 ; CHECK-DAG: st.w [[R1]], 0($4) 38 ; CHECK: .size false_v2f64 39} 40 41define void @oeq_v4f32(<4 x i32>* %c, <4 x float>* %a, <4 x float>* %b) nounwind { 42 ; CHECK: oeq_v4f32: 43 44 %1 = load <4 x float>* %a 45 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5) 46 %2 = load <4 x float>* %b 47 ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6) 48 %3 = fcmp oeq <4 x float> %1, %2 49 %4 = sext <4 x i1> %3 to <4 x i32> 50 ; CHECK-DAG: fceq.w [[R3:\$w[0-9]+]], [[R1]], [[R2]] 51 store <4 x i32> %4, <4 x i32>* %c 52 ; CHECK-DAG: st.w [[R3]], 0($4) 53 54 ret void 55 ; CHECK: .size oeq_v4f32 56} 57 58define void @oeq_v2f64(<2 x i64>* %c, <2 x double>* %a, <2 x double>* %b) nounwind { 59 ; CHECK: oeq_v2f64: 60 61 %1 = load <2 x double>* %a 62 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5) 63 %2 = load <2 x double>* %b 64 ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6) 65 %3 = fcmp oeq <2 x double> %1, %2 66 %4 = sext <2 x i1> %3 to <2 x i64> 67 ; CHECK-DAG: fceq.d [[R3:\$w[0-9]+]], [[R1]], [[R2]] 68 store <2 x i64> %4, <2 x i64>* %c 69 ; CHECK-DAG: st.d [[R3]], 0($4) 70 71 ret void 72 ; CHECK: .size oeq_v2f64 73} 74 75define void @oge_v4f32(<4 x i32>* %c, <4 x float>* %a, <4 x float>* %b) nounwind { 76 ; CHECK: oge_v4f32: 77 78 %1 = load <4 x float>* %a 79 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5) 80 %2 = load <4 x float>* %b 81 ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6) 82 %3 = fcmp oge <4 x float> %1, %2 83 %4 = sext <4 x i1> %3 to <4 x i32> 84 ; CHECK-DAG: fcle.w [[R3:\$w[0-9]+]], [[R2]], [[R1]] 85 store <4 x i32> %4, <4 x i32>* %c 86 ; CHECK-DAG: st.w [[R3]], 0($4) 87 88 ret void 89 ; CHECK: .size oge_v4f32 90} 91 92define void @oge_v2f64(<2 x i64>* %c, <2 x double>* %a, <2 x double>* %b) nounwind { 93 ; CHECK: oge_v2f64: 94 95 %1 = load <2 x double>* %a 96 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5) 97 %2 = load <2 x double>* %b 98 ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6) 99 %3 = fcmp oge <2 x double> %1, %2 100 %4 = sext <2 x i1> %3 to <2 x i64> 101 ; CHECK-DAG: fcle.d [[R3:\$w[0-9]+]], [[R2]], [[R1]] 102 store <2 x i64> %4, <2 x i64>* %c 103 ; CHECK-DAG: st.d [[R3]], 0($4) 104 105 ret void 106 ; CHECK: .size oge_v2f64 107} 108 109define void @ogt_v4f32(<4 x i32>* %c, <4 x float>* %a, <4 x float>* %b) nounwind { 110 ; CHECK: ogt_v4f32: 111 112 %1 = load <4 x float>* %a 113 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5) 114 %2 = load <4 x float>* %b 115 ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6) 116 %3 = fcmp ogt <4 x float> %1, %2 117 %4 = sext <4 x i1> %3 to <4 x i32> 118 ; CHECK-DAG: fclt.w [[R3:\$w[0-9]+]], [[R2]], [[R1]] 119 store <4 x i32> %4, <4 x i32>* %c 120 ; CHECK-DAG: st.w [[R3]], 0($4) 121 122 ret void 123 ; CHECK: .size ogt_v4f32 124} 125 126define void @ogt_v2f64(<2 x i64>* %c, <2 x double>* %a, <2 x double>* %b) nounwind { 127 ; CHECK: ogt_v2f64: 128 129 %1 = load <2 x double>* %a 130 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5) 131 %2 = load <2 x double>* %b 132 ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6) 133 %3 = fcmp ogt <2 x double> %1, %2 134 %4 = sext <2 x i1> %3 to <2 x i64> 135 ; CHECK-DAG: fclt.d [[R3:\$w[0-9]+]], [[R2]], [[R1]] 136 store <2 x i64> %4, <2 x i64>* %c 137 ; CHECK-DAG: st.d [[R3]], 0($4) 138 139 ret void 140 ; CHECK: .size ogt_v2f64 141} 142 143define void @ole_v4f32(<4 x i32>* %c, <4 x float>* %a, <4 x float>* %b) nounwind { 144 ; CHECK: ole_v4f32: 145 146 %1 = load <4 x float>* %a 147 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5) 148 %2 = load <4 x float>* %b 149 ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6) 150 %3 = fcmp ole <4 x float> %1, %2 151 %4 = sext <4 x i1> %3 to <4 x i32> 152 ; CHECK-DAG: fcle.w [[R3:\$w[0-9]+]], [[R1]], [[R2]] 153 store <4 x i32> %4, <4 x i32>* %c 154 ; CHECK-DAG: st.w [[R3]], 0($4) 155 156 ret void 157 ; CHECK: .size ole_v4f32 158} 159 160define void @ole_v2f64(<2 x i64>* %c, <2 x double>* %a, <2 x double>* %b) nounwind { 161 ; CHECK: ole_v2f64: 162 163 %1 = load <2 x double>* %a 164 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5) 165 %2 = load <2 x double>* %b 166 ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6) 167 %3 = fcmp ole <2 x double> %1, %2 168 %4 = sext <2 x i1> %3 to <2 x i64> 169 ; CHECK-DAG: fcle.d [[R3:\$w[0-9]+]], [[R1]], [[R2]] 170 store <2 x i64> %4, <2 x i64>* %c 171 ; CHECK-DAG: st.d [[R3]], 0($4) 172 173 ret void 174 ; CHECK: .size ole_v2f64 175} 176 177define void @olt_v4f32(<4 x i32>* %c, <4 x float>* %a, <4 x float>* %b) nounwind { 178 ; CHECK: olt_v4f32: 179 180 %1 = load <4 x float>* %a 181 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5) 182 %2 = load <4 x float>* %b 183 ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6) 184 %3 = fcmp olt <4 x float> %1, %2 185 %4 = sext <4 x i1> %3 to <4 x i32> 186 ; CHECK-DAG: fclt.w [[R3:\$w[0-9]+]], [[R1]], [[R2]] 187 store <4 x i32> %4, <4 x i32>* %c 188 ; CHECK-DAG: st.w [[R3]], 0($4) 189 190 ret void 191 ; CHECK: .size olt_v4f32 192} 193 194define void @olt_v2f64(<2 x i64>* %c, <2 x double>* %a, <2 x double>* %b) nounwind { 195 ; CHECK: olt_v2f64: 196 197 %1 = load <2 x double>* %a 198 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5) 199 %2 = load <2 x double>* %b 200 ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6) 201 %3 = fcmp olt <2 x double> %1, %2 202 %4 = sext <2 x i1> %3 to <2 x i64> 203 ; CHECK-DAG: fclt.d [[R3:\$w[0-9]+]], [[R1]], [[R2]] 204 store <2 x i64> %4, <2 x i64>* %c 205 ; CHECK-DAG: st.d [[R3]], 0($4) 206 207 ret void 208 ; CHECK: .size olt_v2f64 209} 210 211define void @one_v4f32(<4 x i32>* %c, <4 x float>* %a, <4 x float>* %b) nounwind { 212 ; CHECK: one_v4f32: 213 214 %1 = load <4 x float>* %a 215 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5) 216 %2 = load <4 x float>* %b 217 ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6) 218 %3 = fcmp one <4 x float> %1, %2 219 %4 = sext <4 x i1> %3 to <4 x i32> 220 ; CHECK-DAG: fcne.w [[R3:\$w[0-9]+]], [[R1]], [[R2]] 221 store <4 x i32> %4, <4 x i32>* %c 222 ; CHECK-DAG: st.w [[R3]], 0($4) 223 224 ret void 225 ; CHECK: .size one_v4f32 226} 227 228define void @one_v2f64(<2 x i64>* %c, <2 x double>* %a, <2 x double>* %b) nounwind { 229 ; CHECK: one_v2f64: 230 231 %1 = load <2 x double>* %a 232 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5) 233 %2 = load <2 x double>* %b 234 ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6) 235 %3 = fcmp one <2 x double> %1, %2 236 %4 = sext <2 x i1> %3 to <2 x i64> 237 ; CHECK-DAG: fcne.d [[R3:\$w[0-9]+]], [[R1]], [[R2]] 238 store <2 x i64> %4, <2 x i64>* %c 239 ; CHECK-DAG: st.d [[R3]], 0($4) 240 241 ret void 242 ; CHECK: .size one_v2f64 243} 244 245define void @ord_v4f32(<4 x i32>* %c, <4 x float>* %a, <4 x float>* %b) nounwind { 246 ; CHECK: ord_v4f32: 247 248 %1 = load <4 x float>* %a 249 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5) 250 %2 = load <4 x float>* %b 251 ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6) 252 %3 = fcmp ord <4 x float> %1, %2 253 %4 = sext <4 x i1> %3 to <4 x i32> 254 ; CHECK-DAG: fcor.w [[R3:\$w[0-9]+]], [[R1]], [[R2]] 255 store <4 x i32> %4, <4 x i32>* %c 256 ; CHECK-DAG: st.w [[R3]], 0($4) 257 258 ret void 259 ; CHECK: .size ord_v4f32 260} 261 262define void @ord_v2f64(<2 x i64>* %c, <2 x double>* %a, <2 x double>* %b) nounwind { 263 ; CHECK: ord_v2f64: 264 265 %1 = load <2 x double>* %a 266 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5) 267 %2 = load <2 x double>* %b 268 ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6) 269 %3 = fcmp ord <2 x double> %1, %2 270 %4 = sext <2 x i1> %3 to <2 x i64> 271 ; CHECK-DAG: fcor.d [[R3:\$w[0-9]+]], [[R1]], [[R2]] 272 store <2 x i64> %4, <2 x i64>* %c 273 ; CHECK-DAG: st.d [[R3]], 0($4) 274 275 ret void 276 ; CHECK: .size ord_v2f64 277} 278 279define void @ueq_v4f32(<4 x i32>* %c, <4 x float>* %a, <4 x float>* %b) nounwind { 280 ; CHECK: ueq_v4f32: 281 282 %1 = load <4 x float>* %a 283 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5) 284 %2 = load <4 x float>* %b 285 ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6) 286 %3 = fcmp ueq <4 x float> %1, %2 287 %4 = sext <4 x i1> %3 to <4 x i32> 288 ; CHECK-DAG: fcueq.w [[R3:\$w[0-9]+]], [[R1]], [[R2]] 289 store <4 x i32> %4, <4 x i32>* %c 290 ; CHECK-DAG: st.w [[R3]], 0($4) 291 292 ret void 293 ; CHECK: .size ueq_v4f32 294} 295 296define void @ueq_v2f64(<2 x i64>* %c, <2 x double>* %a, <2 x double>* %b) nounwind { 297 ; CHECK: ueq_v2f64: 298 299 %1 = load <2 x double>* %a 300 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5) 301 %2 = load <2 x double>* %b 302 ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6) 303 %3 = fcmp ueq <2 x double> %1, %2 304 %4 = sext <2 x i1> %3 to <2 x i64> 305 ; CHECK-DAG: fcueq.d [[R3:\$w[0-9]+]], [[R1]], [[R2]] 306 store <2 x i64> %4, <2 x i64>* %c 307 ; CHECK-DAG: st.d [[R3]], 0($4) 308 309 ret void 310 ; CHECK: .size ueq_v2f64 311} 312 313define void @uge_v4f32(<4 x i32>* %c, <4 x float>* %a, <4 x float>* %b) nounwind { 314 ; CHECK: uge_v4f32: 315 316 %1 = load <4 x float>* %a 317 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5) 318 %2 = load <4 x float>* %b 319 ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6) 320 %3 = fcmp uge <4 x float> %1, %2 321 %4 = sext <4 x i1> %3 to <4 x i32> 322 ; CHECK-DAG: fcule.w [[R3:\$w[0-9]+]], [[R2]], [[R1]] 323 store <4 x i32> %4, <4 x i32>* %c 324 ; CHECK-DAG: st.w [[R3]], 0($4) 325 326 ret void 327 ; CHECK: .size uge_v4f32 328} 329 330define void @uge_v2f64(<2 x i64>* %c, <2 x double>* %a, <2 x double>* %b) nounwind { 331 ; CHECK: uge_v2f64: 332 333 %1 = load <2 x double>* %a 334 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5) 335 %2 = load <2 x double>* %b 336 ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6) 337 %3 = fcmp uge <2 x double> %1, %2 338 %4 = sext <2 x i1> %3 to <2 x i64> 339 ; CHECK-DAG: fcule.d [[R3:\$w[0-9]+]], [[R2]], [[R1]] 340 store <2 x i64> %4, <2 x i64>* %c 341 ; CHECK-DAG: st.d [[R3]], 0($4) 342 343 ret void 344 ; CHECK: .size uge_v2f64 345} 346 347define void @ugt_v4f32(<4 x i32>* %c, <4 x float>* %a, <4 x float>* %b) nounwind { 348 ; CHECK: ugt_v4f32: 349 350 %1 = load <4 x float>* %a 351 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5) 352 %2 = load <4 x float>* %b 353 ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6) 354 %3 = fcmp ugt <4 x float> %1, %2 355 %4 = sext <4 x i1> %3 to <4 x i32> 356 ; CHECK-DAG: fcult.w [[R3:\$w[0-9]+]], [[R2]], [[R1]] 357 store <4 x i32> %4, <4 x i32>* %c 358 ; CHECK-DAG: st.w [[R3]], 0($4) 359 360 ret void 361 ; CHECK: .size ugt_v4f32 362} 363 364define void @ugt_v2f64(<2 x i64>* %c, <2 x double>* %a, <2 x double>* %b) nounwind { 365 ; CHECK: ugt_v2f64: 366 367 %1 = load <2 x double>* %a 368 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5) 369 %2 = load <2 x double>* %b 370 ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6) 371 %3 = fcmp ugt <2 x double> %1, %2 372 %4 = sext <2 x i1> %3 to <2 x i64> 373 ; CHECK-DAG: fcult.d [[R3:\$w[0-9]+]], [[R2]], [[R1]] 374 store <2 x i64> %4, <2 x i64>* %c 375 ; CHECK-DAG: st.d [[R3]], 0($4) 376 377 ret void 378 ; CHECK: .size ugt_v2f64 379} 380 381define void @ule_v4f32(<4 x i32>* %c, <4 x float>* %a, <4 x float>* %b) nounwind { 382 ; CHECK: ule_v4f32: 383 384 %1 = load <4 x float>* %a 385 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5) 386 %2 = load <4 x float>* %b 387 ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6) 388 %3 = fcmp ule <4 x float> %1, %2 389 %4 = sext <4 x i1> %3 to <4 x i32> 390 ; CHECK-DAG: fcule.w [[R3:\$w[0-9]+]], [[R1]], [[R2]] 391 store <4 x i32> %4, <4 x i32>* %c 392 ; CHECK-DAG: st.w [[R3]], 0($4) 393 394 ret void 395 ; CHECK: .size ule_v4f32 396} 397 398define void @ule_v2f64(<2 x i64>* %c, <2 x double>* %a, <2 x double>* %b) nounwind { 399 ; CHECK: ule_v2f64: 400 401 %1 = load <2 x double>* %a 402 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5) 403 %2 = load <2 x double>* %b 404 ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6) 405 %3 = fcmp ule <2 x double> %1, %2 406 %4 = sext <2 x i1> %3 to <2 x i64> 407 ; CHECK-DAG: fcule.d [[R3:\$w[0-9]+]], [[R1]], [[R2]] 408 store <2 x i64> %4, <2 x i64>* %c 409 ; CHECK-DAG: st.d [[R3]], 0($4) 410 411 ret void 412 ; CHECK: .size ule_v2f64 413} 414 415define void @ult_v4f32(<4 x i32>* %c, <4 x float>* %a, <4 x float>* %b) nounwind { 416 ; CHECK: ult_v4f32: 417 418 %1 = load <4 x float>* %a 419 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5) 420 %2 = load <4 x float>* %b 421 ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6) 422 %3 = fcmp ult <4 x float> %1, %2 423 %4 = sext <4 x i1> %3 to <4 x i32> 424 ; CHECK-DAG: fcult.w [[R3:\$w[0-9]+]], [[R1]], [[R2]] 425 store <4 x i32> %4, <4 x i32>* %c 426 ; CHECK-DAG: st.w [[R3]], 0($4) 427 428 ret void 429 ; CHECK: .size ult_v4f32 430} 431 432define void @ult_v2f64(<2 x i64>* %c, <2 x double>* %a, <2 x double>* %b) nounwind { 433 ; CHECK: ult_v2f64: 434 435 %1 = load <2 x double>* %a 436 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5) 437 %2 = load <2 x double>* %b 438 ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6) 439 %3 = fcmp ult <2 x double> %1, %2 440 %4 = sext <2 x i1> %3 to <2 x i64> 441 ; CHECK-DAG: fcult.d [[R3:\$w[0-9]+]], [[R1]], [[R2]] 442 store <2 x i64> %4, <2 x i64>* %c 443 ; CHECK-DAG: st.d [[R3]], 0($4) 444 445 ret void 446 ; CHECK: .size ult_v2f64 447} 448 449define void @uno_v4f32(<4 x i32>* %c, <4 x float>* %a, <4 x float>* %b) nounwind { 450 ; CHECK: uno_v4f32: 451 452 %1 = load <4 x float>* %a 453 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5) 454 %2 = load <4 x float>* %b 455 ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6) 456 %3 = fcmp uno <4 x float> %1, %2 457 %4 = sext <4 x i1> %3 to <4 x i32> 458 ; CHECK-DAG: fcun.w [[R3:\$w[0-9]+]], [[R1]], [[R2]] 459 store <4 x i32> %4, <4 x i32>* %c 460 ; CHECK-DAG: st.w [[R3]], 0($4) 461 462 ret void 463 ; CHECK: .size uno_v4f32 464} 465 466define void @uno_v2f64(<2 x i64>* %c, <2 x double>* %a, <2 x double>* %b) nounwind { 467 ; CHECK: uno_v2f64: 468 469 %1 = load <2 x double>* %a 470 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5) 471 %2 = load <2 x double>* %b 472 ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6) 473 %3 = fcmp uno <2 x double> %1, %2 474 %4 = sext <2 x i1> %3 to <2 x i64> 475 ; CHECK-DAG: fcun.d [[R3:\$w[0-9]+]], [[R1]], [[R2]] 476 store <2 x i64> %4, <2 x i64>* %c 477 ; CHECK-DAG: st.d [[R3]], 0($4) 478 479 ret void 480 ; CHECK: .size uno_v2f64 481} 482 483define void @true_v4f32(<4 x i32>* %c, <4 x float>* %a, <4 x float>* %b) nounwind { 484 ; CHECK: true_v4f32: 485 486 %1 = load <4 x float>* %a 487 %2 = load <4 x float>* %b 488 %3 = fcmp true <4 x float> %1, %2 489 %4 = sext <4 x i1> %3 to <4 x i32> 490 store <4 x i32> %4, <4 x i32>* %c 491 ret void 492 493 ; (setcc $a, $b, SETTRUE) is always folded, so we won't get fcaf: 494 ; CHECK-DAG: ldi.b [[R1:\$w[0-9]+]], -1 495 ; CHECK-DAG: st.w [[R1]], 0($4) 496 ; CHECK: .size true_v4f32 497} 498 499define void @true_v2f64(<2 x i64>* %c, <2 x double>* %a, <2 x double>* %b) nounwind { 500 ; CHECK: true_v2f64: 501 502 %1 = load <2 x double>* %a 503 %2 = load <2 x double>* %b 504 %3 = fcmp true <2 x double> %1, %2 505 %4 = sext <2 x i1> %3 to <2 x i64> 506 store <2 x i64> %4, <2 x i64>* %c 507 ret void 508 509 ; (setcc $a, $b, SETTRUE) is always folded. 510 ; CHECK-DAG: ldi.b [[R1:\$w[0-9]+]], -1 511 ; CHECK-DAG: st.w [[R1]], 0($4) 512 ; CHECK: .size true_v2f64 513} 514 515define void @bsel_v4f32(<4 x float>* %d, <4 x float>* %a, <4 x float>* %b, 516 <4 x float>* %c) nounwind { 517 ; CHECK: bsel_v4f32: 518 519 %1 = load <4 x float>* %a 520 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5) 521 %2 = load <4 x float>* %b 522 ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6) 523 %3 = load <4 x float>* %c 524 ; CHECK-DAG: ld.w [[R3:\$w[0-9]+]], 0($7) 525 %4 = fcmp ogt <4 x float> %1, %2 526 ; CHECK-DAG: fclt.w [[R4:\$w[0-9]+]], [[R2]], [[R1]] 527 %5 = select <4 x i1> %4, <4 x float> %1, <4 x float> %3 528 ; Note that IfSet and IfClr are swapped since the condition is inverted 529 ; CHECK-DAG: bsel.v [[R4]], [[R3]], [[R1]] 530 store <4 x float> %5, <4 x float>* %d 531 ; CHECK-DAG: st.w [[R4]], 0($4) 532 533 ret void 534 ; CHECK: .size bsel_v4f32 535} 536 537define void @bsel_v2f64(<2 x double>* %d, <2 x double>* %a, <2 x double>* %b, 538 <2 x double>* %c) nounwind { 539 ; CHECK: bsel_v2f64: 540 541 %1 = load <2 x double>* %a 542 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5) 543 %2 = load <2 x double>* %b 544 ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6) 545 %3 = load <2 x double>* %c 546 ; CHECK-DAG: ld.d [[R3:\$w[0-9]+]], 0($7) 547 %4 = fcmp ogt <2 x double> %1, %2 548 ; CHECK-DAG: fclt.d [[R4:\$w[0-9]+]], [[R2]], [[R1]] 549 %5 = select <2 x i1> %4, <2 x double> %1, <2 x double> %3 550 ; Note that IfSet and IfClr are swapped since the condition is inverted 551 ; CHECK-DAG: bsel.v [[R4]], [[R3]], [[R1]] 552 store <2 x double> %5, <2 x double>* %d 553 ; CHECK-DAG: st.d [[R4]], 0($4) 554 555 ret void 556 ; CHECK: .size bsel_v2f64 557} 558 559define void @bseli_v4f32(<4 x float>* %d, <4 x float>* %a, <4 x float>* %b, 560 <4 x float>* %c) nounwind { 561 ; CHECK: bseli_v4f32: 562 563 %1 = load <4 x float>* %a 564 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5) 565 %2 = load <4 x float>* %b 566 ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6) 567 %3 = fcmp ogt <4 x float> %1, %2 568 ; CHECK-DAG: fclt.w [[R4:\$w[0-9]+]], [[R2]], [[R1]] 569 %4 = select <4 x i1> %3, <4 x float> %1, <4 x float> zeroinitializer 570 ; Note that IfSet and IfClr are swapped since the condition is inverted 571 ; CHECK-DAG: bsel.v [[R4]], [[R3:\$w[0-9]+]], [[R1]] 572 store <4 x float> %4, <4 x float>* %d 573 ; CHECK-DAG: st.w [[R4]], 0($4) 574 575 ret void 576 ; CHECK: .size bseli_v4f32 577} 578 579define void @bseli_v2f64(<2 x double>* %d, <2 x double>* %a, <2 x double>* %b, 580 <2 x double>* %c) nounwind { 581 ; CHECK: bseli_v2f64: 582 583 %1 = load <2 x double>* %a 584 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5) 585 %2 = load <2 x double>* %b 586 ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6) 587 %3 = fcmp ogt <2 x double> %1, %2 588 ; CHECK-DAG: fclt.d [[R4:\$w[0-9]+]], [[R2]], [[R1]] 589 %4 = select <2 x i1> %3, <2 x double> %1, <2 x double> zeroinitializer 590 ; Note that IfSet and IfClr are swapped since the condition is inverted 591 ; CHECK-DAG: bsel.v [[R4]], [[R3:\$w[0-9]+]], [[R1]] 592 store <2 x double> %4, <2 x double>* %d 593 ; CHECK-DAG: st.d [[R4]], 0($4) 594 595 ret void 596 ; CHECK: .size bseli_v2f64 597} 598 599define void @max_v4f32(<4 x float>* %c, <4 x float>* %a, <4 x float>* %b) nounwind { 600 ; CHECK: max_v4f32: 601 602 %1 = load <4 x float>* %a 603 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5) 604 %2 = load <4 x float>* %b 605 ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6) 606 %3 = tail call <4 x float> @llvm.mips.fmax.w(<4 x float> %1, <4 x float> %2) 607 ; CHECK-DAG: fmax.w [[R3:\$w[0-9]+]], [[R1]], [[R2]] 608 store <4 x float> %3, <4 x float>* %c 609 ; CHECK-DAG: st.w [[R3]], 0($4) 610 611 ret void 612 ; CHECK: .size max_v4f32 613} 614 615define void @max_v2f64(<2 x double>* %c, <2 x double>* %a, <2 x double>* %b) nounwind { 616 ; CHECK: max_v2f64: 617 618 %1 = load <2 x double>* %a 619 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5) 620 %2 = load <2 x double>* %b 621 ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6) 622 %3 = tail call <2 x double> @llvm.mips.fmax.d(<2 x double> %1, <2 x double> %2) 623 ; CHECK-DAG: fmax.d [[R3:\$w[0-9]+]], [[R1]], [[R2]] 624 store <2 x double> %3, <2 x double>* %c 625 ; CHECK-DAG: st.d [[R3]], 0($4) 626 627 ret void 628 ; CHECK: .size max_v2f64 629} 630 631define void @min_v4f32(<4 x float>* %c, <4 x float>* %a, <4 x float>* %b) nounwind { 632 ; CHECK: min_v4f32: 633 634 %1 = load <4 x float>* %a 635 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5) 636 %2 = load <4 x float>* %b 637 ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6) 638 %3 = tail call <4 x float> @llvm.mips.fmin.w(<4 x float> %1, <4 x float> %2) 639 ; CHECK-DAG: fmin.w [[R3:\$w[0-9]+]], [[R1]], [[R2]] 640 store <4 x float> %3, <4 x float>* %c 641 ; CHECK-DAG: st.w [[R3]], 0($4) 642 643 ret void 644 ; CHECK: .size min_v4f32 645} 646 647define void @min_v2f64(<2 x double>* %c, <2 x double>* %a, <2 x double>* %b) nounwind { 648 ; CHECK: min_v2f64: 649 650 %1 = load <2 x double>* %a 651 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5) 652 %2 = load <2 x double>* %b 653 ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6) 654 %3 = tail call <2 x double> @llvm.mips.fmin.d(<2 x double> %1, <2 x double> %2) 655 ; CHECK-DAG: fmin.d [[R3:\$w[0-9]+]], [[R1]], [[R2]] 656 store <2 x double> %3, <2 x double>* %c 657 ; CHECK-DAG: st.d [[R3]], 0($4) 658 659 ret void 660 ; CHECK: .size min_v2f64 661} 662