1; Test the MSA element insertion intrinsics that are encoded with the ELM 2; instruction format. 3 4; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s 5; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s 6 7@llvm_mips_insert_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 8@llvm_mips_insert_b_ARG3 = global i32 27, align 16 9@llvm_mips_insert_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16 10 11define void @llvm_mips_insert_b_test() nounwind { 12entry: 13 %0 = load <16 x i8>* @llvm_mips_insert_b_ARG1 14 %1 = load i32* @llvm_mips_insert_b_ARG3 15 %2 = tail call <16 x i8> @llvm.mips.insert.b(<16 x i8> %0, i32 1, i32 %1) 16 store <16 x i8> %2, <16 x i8>* @llvm_mips_insert_b_RES 17 ret void 18} 19 20declare <16 x i8> @llvm.mips.insert.b(<16 x i8>, i32, i32) nounwind 21 22; CHECK: llvm_mips_insert_b_test: 23; CHECK-DAG: lw [[R1:\$[0-9]+]], 0( 24; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0( 25; CHECK-DAG: insert.b [[R2]][1], [[R1]] 26; CHECK-DAG: st.b [[R2]], 0( 27; CHECK: .size llvm_mips_insert_b_test 28; 29@llvm_mips_insert_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16 30@llvm_mips_insert_h_ARG3 = global i32 27, align 16 31@llvm_mips_insert_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16 32 33define void @llvm_mips_insert_h_test() nounwind { 34entry: 35 %0 = load <8 x i16>* @llvm_mips_insert_h_ARG1 36 %1 = load i32* @llvm_mips_insert_h_ARG3 37 %2 = tail call <8 x i16> @llvm.mips.insert.h(<8 x i16> %0, i32 1, i32 %1) 38 store <8 x i16> %2, <8 x i16>* @llvm_mips_insert_h_RES 39 ret void 40} 41 42declare <8 x i16> @llvm.mips.insert.h(<8 x i16>, i32, i32) nounwind 43 44; CHECK: llvm_mips_insert_h_test: 45; CHECK-DAG: lw [[R1:\$[0-9]+]], 0( 46; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0( 47; CHECK-DAG: insert.h [[R2]][1], [[R1]] 48; CHECK-DAG: st.h [[R2]], 0( 49; CHECK: .size llvm_mips_insert_h_test 50; 51@llvm_mips_insert_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16 52@llvm_mips_insert_w_ARG3 = global i32 27, align 16 53@llvm_mips_insert_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16 54 55define void @llvm_mips_insert_w_test() nounwind { 56entry: 57 %0 = load <4 x i32>* @llvm_mips_insert_w_ARG1 58 %1 = load i32* @llvm_mips_insert_w_ARG3 59 %2 = tail call <4 x i32> @llvm.mips.insert.w(<4 x i32> %0, i32 1, i32 %1) 60 store <4 x i32> %2, <4 x i32>* @llvm_mips_insert_w_RES 61 ret void 62} 63 64declare <4 x i32> @llvm.mips.insert.w(<4 x i32>, i32, i32) nounwind 65 66; CHECK: llvm_mips_insert_w_test: 67; CHECK-DAG: lw [[R1:\$[0-9]+]], 0( 68; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0( 69; CHECK-DAG: insert.w [[R2]][1], [[R1]] 70; CHECK-DAG: st.w [[R2]], 0( 71; CHECK: .size llvm_mips_insert_w_test 72; 73@llvm_mips_insert_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16 74@llvm_mips_insert_d_ARG3 = global i64 27, align 16 75@llvm_mips_insert_d_RES = global <2 x i64> <i64 0, i64 0>, align 16 76 77define void @llvm_mips_insert_d_test() nounwind { 78entry: 79 %0 = load <2 x i64>* @llvm_mips_insert_d_ARG1 80 %1 = load i64* @llvm_mips_insert_d_ARG3 81 %2 = tail call <2 x i64> @llvm.mips.insert.d(<2 x i64> %0, i32 1, i64 %1) 82 store <2 x i64> %2, <2 x i64>* @llvm_mips_insert_d_RES 83 ret void 84} 85 86declare <2 x i64> @llvm.mips.insert.d(<2 x i64>, i32, i64) nounwind 87 88; CHECK: llvm_mips_insert_d_test: 89; CHECK-DAG: lw [[R1:\$[0-9]+]], 0( 90; CHECK-DAG: lw [[R2:\$[0-9]+]], 4( 91; CHECK-DAG: ld.w [[R3:\$w[0-9]+]], 92; CHECK-DAG: insert.w [[R3]][2], [[R1]] 93; CHECK-DAG: insert.w [[R3]][3], [[R2]] 94; CHECK-DAG: st.w [[R3]], 95; CHECK: .size llvm_mips_insert_d_test 96; 97@llvm_mips_insve_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 98@llvm_mips_insve_b_ARG3 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16 99@llvm_mips_insve_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16 100 101define void @llvm_mips_insve_b_test() nounwind { 102entry: 103 %0 = load <16 x i8>* @llvm_mips_insve_b_ARG1 104 %1 = load <16 x i8>* @llvm_mips_insve_b_ARG3 105 %2 = tail call <16 x i8> @llvm.mips.insve.b(<16 x i8> %0, i32 1, <16 x i8> %1) 106 store <16 x i8> %2, <16 x i8>* @llvm_mips_insve_b_RES 107 ret void 108} 109 110declare <16 x i8> @llvm.mips.insve.b(<16 x i8>, i32, <16 x i8>) nounwind 111 112; CHECK: llvm_mips_insve_b_test: 113; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_insve_b_ARG1)( 114; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_insve_b_ARG3)( 115; CHECK-DAG: ld.b [[R3:\$w[0-9]+]], 0([[R1]]) 116; CHECK-DAG: ld.b [[R4:\$w[0-9]+]], 0([[R2]]) 117; CHECK-DAG: insve.b [[R3]][1], [[R4]][0] 118; CHECK-DAG: st.b [[R3]], 119; CHECK: .size llvm_mips_insve_b_test 120; 121@llvm_mips_insve_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16 122@llvm_mips_insve_h_ARG3 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16 123@llvm_mips_insve_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16 124 125define void @llvm_mips_insve_h_test() nounwind { 126entry: 127 %0 = load <8 x i16>* @llvm_mips_insve_h_ARG1 128 %1 = load <8 x i16>* @llvm_mips_insve_h_ARG3 129 %2 = tail call <8 x i16> @llvm.mips.insve.h(<8 x i16> %0, i32 1, <8 x i16> %1) 130 store <8 x i16> %2, <8 x i16>* @llvm_mips_insve_h_RES 131 ret void 132} 133 134declare <8 x i16> @llvm.mips.insve.h(<8 x i16>, i32, <8 x i16>) nounwind 135 136; CHECK: llvm_mips_insve_h_test: 137; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_insve_h_ARG1)( 138; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_insve_h_ARG3)( 139; CHECK-DAG: ld.h [[R3:\$w[0-9]+]], 0([[R1]]) 140; CHECK-DAG: ld.h [[R4:\$w[0-9]+]], 0([[R2]]) 141; CHECK-DAG: insve.h [[R3]][1], [[R4]][0] 142; CHECK-DAG: st.h [[R3]], 143; CHECK: .size llvm_mips_insve_h_test 144; 145@llvm_mips_insve_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16 146@llvm_mips_insve_w_ARG3 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16 147@llvm_mips_insve_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16 148 149define void @llvm_mips_insve_w_test() nounwind { 150entry: 151 %0 = load <4 x i32>* @llvm_mips_insve_w_ARG1 152 %1 = load <4 x i32>* @llvm_mips_insve_w_ARG3 153 %2 = tail call <4 x i32> @llvm.mips.insve.w(<4 x i32> %0, i32 1, <4 x i32> %1) 154 store <4 x i32> %2, <4 x i32>* @llvm_mips_insve_w_RES 155 ret void 156} 157 158declare <4 x i32> @llvm.mips.insve.w(<4 x i32>, i32, <4 x i32>) nounwind 159 160; CHECK: llvm_mips_insve_w_test: 161; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_insve_w_ARG1)( 162; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_insve_w_ARG3)( 163; CHECK-DAG: ld.w [[R3:\$w[0-9]+]], 0([[R1]]) 164; CHECK-DAG: ld.w [[R4:\$w[0-9]+]], 0([[R2]]) 165; CHECK-DAG: insve.w [[R3]][1], [[R4]][0] 166; CHECK-DAG: st.w [[R3]], 167; CHECK: .size llvm_mips_insve_w_test 168; 169@llvm_mips_insve_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16 170@llvm_mips_insve_d_ARG3 = global <2 x i64> <i64 2, i64 3>, align 16 171@llvm_mips_insve_d_RES = global <2 x i64> <i64 0, i64 0>, align 16 172 173define void @llvm_mips_insve_d_test() nounwind { 174entry: 175 %0 = load <2 x i64>* @llvm_mips_insve_d_ARG1 176 %1 = load <2 x i64>* @llvm_mips_insve_d_ARG3 177 %2 = tail call <2 x i64> @llvm.mips.insve.d(<2 x i64> %0, i32 1, <2 x i64> %1) 178 store <2 x i64> %2, <2 x i64>* @llvm_mips_insve_d_RES 179 ret void 180} 181 182declare <2 x i64> @llvm.mips.insve.d(<2 x i64>, i32, <2 x i64>) nounwind 183 184; CHECK: llvm_mips_insve_d_test: 185; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_insve_d_ARG1)( 186; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_insve_d_ARG3)( 187; CHECK-DAG: ld.d [[R3:\$w[0-9]+]], 0([[R1]]) 188; CHECK-DAG: ld.d [[R4:\$w[0-9]+]], 0([[R2]]) 189; CHECK-DAG: insve.d [[R3]][1], [[R4]][0] 190; CHECK-DAG: st.d [[R3]], 191; CHECK: .size llvm_mips_insve_d_test 192; 193