1; Test the MSA intrinsics that are encoded with the ELM instruction format and 2; are either shifts or slides. 3 4; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s 5; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s 6 7@llvm_mips_sldi_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 8@llvm_mips_sldi_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16 9 10define void @llvm_mips_sldi_b_test() nounwind { 11entry: 12 %0 = load <16 x i8>* @llvm_mips_sldi_b_ARG1 13 %1 = tail call <16 x i8> @llvm.mips.sldi.b(<16 x i8> %0, i32 1) 14 store <16 x i8> %1, <16 x i8>* @llvm_mips_sldi_b_RES 15 ret void 16} 17 18declare <16 x i8> @llvm.mips.sldi.b(<16 x i8>, i32) nounwind 19 20; CHECK: llvm_mips_sldi_b_test: 21; CHECK: ld.b 22; CHECK: sldi.b 23; CHECK: st.b 24; CHECK: .size llvm_mips_sldi_b_test 25; 26@llvm_mips_sldi_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16 27@llvm_mips_sldi_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16 28 29define void @llvm_mips_sldi_h_test() nounwind { 30entry: 31 %0 = load <8 x i16>* @llvm_mips_sldi_h_ARG1 32 %1 = tail call <8 x i16> @llvm.mips.sldi.h(<8 x i16> %0, i32 1) 33 store <8 x i16> %1, <8 x i16>* @llvm_mips_sldi_h_RES 34 ret void 35} 36 37declare <8 x i16> @llvm.mips.sldi.h(<8 x i16>, i32) nounwind 38 39; CHECK: llvm_mips_sldi_h_test: 40; CHECK: ld.h 41; CHECK: sldi.h 42; CHECK: st.h 43; CHECK: .size llvm_mips_sldi_h_test 44; 45@llvm_mips_sldi_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16 46@llvm_mips_sldi_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16 47 48define void @llvm_mips_sldi_w_test() nounwind { 49entry: 50 %0 = load <4 x i32>* @llvm_mips_sldi_w_ARG1 51 %1 = tail call <4 x i32> @llvm.mips.sldi.w(<4 x i32> %0, i32 1) 52 store <4 x i32> %1, <4 x i32>* @llvm_mips_sldi_w_RES 53 ret void 54} 55 56declare <4 x i32> @llvm.mips.sldi.w(<4 x i32>, i32) nounwind 57 58; CHECK: llvm_mips_sldi_w_test: 59; CHECK: ld.w 60; CHECK: sldi.w 61; CHECK: st.w 62; CHECK: .size llvm_mips_sldi_w_test 63; 64@llvm_mips_sldi_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16 65@llvm_mips_sldi_d_RES = global <2 x i64> <i64 0, i64 0>, align 16 66 67define void @llvm_mips_sldi_d_test() nounwind { 68entry: 69 %0 = load <2 x i64>* @llvm_mips_sldi_d_ARG1 70 %1 = tail call <2 x i64> @llvm.mips.sldi.d(<2 x i64> %0, i32 1) 71 store <2 x i64> %1, <2 x i64>* @llvm_mips_sldi_d_RES 72 ret void 73} 74 75declare <2 x i64> @llvm.mips.sldi.d(<2 x i64>, i32) nounwind 76 77; CHECK: llvm_mips_sldi_d_test: 78; CHECK: ld.d 79; CHECK: sldi.d 80; CHECK: st.d 81; CHECK: .size llvm_mips_sldi_d_test 82; 83@llvm_mips_splati_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 84@llvm_mips_splati_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16 85 86define void @llvm_mips_splati_b_test() nounwind { 87entry: 88 %0 = load <16 x i8>* @llvm_mips_splati_b_ARG1 89 %1 = tail call <16 x i8> @llvm.mips.splati.b(<16 x i8> %0, i32 1) 90 store <16 x i8> %1, <16 x i8>* @llvm_mips_splati_b_RES 91 ret void 92} 93 94declare <16 x i8> @llvm.mips.splati.b(<16 x i8>, i32) nounwind 95 96; CHECK: llvm_mips_splati_b_test: 97; CHECK: ld.b 98; CHECK: splati.b 99; CHECK: st.b 100; CHECK: .size llvm_mips_splati_b_test 101; 102@llvm_mips_splati_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16 103@llvm_mips_splati_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16 104 105define void @llvm_mips_splati_h_test() nounwind { 106entry: 107 %0 = load <8 x i16>* @llvm_mips_splati_h_ARG1 108 %1 = tail call <8 x i16> @llvm.mips.splati.h(<8 x i16> %0, i32 1) 109 store <8 x i16> %1, <8 x i16>* @llvm_mips_splati_h_RES 110 ret void 111} 112 113declare <8 x i16> @llvm.mips.splati.h(<8 x i16>, i32) nounwind 114 115; CHECK: llvm_mips_splati_h_test: 116; CHECK: ld.h 117; CHECK: splati.h 118; CHECK: st.h 119; CHECK: .size llvm_mips_splati_h_test 120; 121@llvm_mips_splati_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16 122@llvm_mips_splati_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16 123 124define void @llvm_mips_splati_w_test() nounwind { 125entry: 126 %0 = load <4 x i32>* @llvm_mips_splati_w_ARG1 127 %1 = tail call <4 x i32> @llvm.mips.splati.w(<4 x i32> %0, i32 1) 128 store <4 x i32> %1, <4 x i32>* @llvm_mips_splati_w_RES 129 ret void 130} 131 132declare <4 x i32> @llvm.mips.splati.w(<4 x i32>, i32) nounwind 133 134; CHECK: llvm_mips_splati_w_test: 135; CHECK: ld.w 136; CHECK: splati.w 137; CHECK: st.w 138; CHECK: .size llvm_mips_splati_w_test 139; 140@llvm_mips_splati_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16 141@llvm_mips_splati_d_RES = global <2 x i64> <i64 0, i64 0>, align 16 142 143define void @llvm_mips_splati_d_test() nounwind { 144entry: 145 %0 = load <2 x i64>* @llvm_mips_splati_d_ARG1 146 %1 = tail call <2 x i64> @llvm.mips.splati.d(<2 x i64> %0, i32 1) 147 store <2 x i64> %1, <2 x i64>* @llvm_mips_splati_d_RES 148 ret void 149} 150 151declare <2 x i64> @llvm.mips.splati.d(<2 x i64>, i32) nounwind 152 153; CHECK: llvm_mips_splati_d_test: 154; CHECK: ld.d 155; CHECK: splati.d 156; CHECK: st.d 157; CHECK: .size llvm_mips_splati_d_test 158; 159