1; RUN: llc < %s | FileCheck %s
2target datalayout = "E-m:e-i64:64-n32:64"
3target triple = "powerpc64-unknown-linux-gnu"
4
5; Stackmap Header: no constants - 6 callsites
6; CHECK-LABEL: .section	.llvm_stackmaps
7; CHECK-NEXT:  __LLVM_StackMaps:
8; Header
9; CHECK-NEXT:   .byte 1
10; CHECK-NEXT:   .byte 0
11; CHECK-NEXT:   .short 0
12; Num Functions
13; CHECK-NEXT:   .long 8
14; Num LargeConstants
15; CHECK-NEXT:   .long 0
16; Num Callsites
17; CHECK-NEXT:   .long 8
18
19; Functions and stack size
20; CHECK-NEXT:   .quad test
21; CHECK-NEXT:   .quad 128
22; CHECK-NEXT:   .quad property_access1
23; CHECK-NEXT:   .quad 128
24; CHECK-NEXT:   .quad property_access2
25; CHECK-NEXT:   .quad 128
26; CHECK-NEXT:   .quad property_access3
27; CHECK-NEXT:   .quad 128
28; CHECK-NEXT:   .quad anyreg_test1
29; CHECK-NEXT:   .quad 160
30; CHECK-NEXT:   .quad anyreg_test2
31; CHECK-NEXT:   .quad 160
32; CHECK-NEXT:   .quad patchpoint_spilldef
33; CHECK-NEXT:   .quad 256
34; CHECK-NEXT:   .quad patchpoint_spillargs
35; CHECK-NEXT:   .quad 288
36
37
38; test
39; CHECK-LABEL:  .long   .L{{.*}}-.L.test
40; CHECK-NEXT:   .short  0
41; 3 locations
42; CHECK-NEXT:   .short  3
43; Loc 0: Register
44; CHECK-NEXT:   .byte 1
45; CHECK-NEXT:   .byte 4
46; CHECK-NEXT:   .short {{[0-9]+}}
47; CHECK-NEXT:   .long 0
48; Loc 1: Register
49; CHECK-NEXT:   .byte 1
50; CHECK-NEXT:   .byte 4
51; CHECK-NEXT:   .short {{[0-9]+}}
52; CHECK-NEXT:   .long 0
53; Loc 2: Constant 3
54; CHECK-NEXT:   .byte 4
55; CHECK-NEXT:   .byte 8
56; CHECK-NEXT:   .short  0
57; CHECK-NEXT:   .long 3
58define i64 @test() nounwind ssp uwtable {
59entry:
60  call anyregcc void (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.void(i64 0, i32 24, i8* null, i32 2, i32 1, i32 2, i64 3)
61  ret i64 0
62}
63
64; property access 1 - %obj is an anyreg call argument and should therefore be in a register
65; CHECK-LABEL:  .long   .L{{.*}}-.L.property_access1
66; CHECK-NEXT:   .short  0
67; 2 locations
68; CHECK-NEXT:   .short  2
69; Loc 0: Register <-- this is the return register
70; CHECK-NEXT:   .byte 1
71; CHECK-NEXT:   .byte 8
72; CHECK-NEXT:   .short {{[0-9]+}}
73; CHECK-NEXT:   .long 0
74; Loc 1: Register
75; CHECK-NEXT:   .byte 1
76; CHECK-NEXT:   .byte 8
77; CHECK-NEXT:   .short {{[0-9]+}}
78; CHECK-NEXT:   .long 0
79define i64 @property_access1(i8* %obj) nounwind ssp uwtable {
80entry:
81  %f = inttoptr i64 281474417671919 to i8*
82  %ret = call anyregcc i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 1, i32 24, i8* %f, i32 1, i8* %obj)
83  ret i64 %ret
84}
85
86; property access 2 - %obj is an anyreg call argument and should therefore be in a register
87; CHECK-LABEL:  .long   .L{{.*}}-.L.property_access2
88; CHECK-NEXT:   .short  0
89; 2 locations
90; CHECK-NEXT:   .short  2
91; Loc 0: Register <-- this is the return register
92; CHECK-NEXT:   .byte 1
93; CHECK-NEXT:   .byte 8
94; CHECK-NEXT:   .short {{[0-9]+}}
95; CHECK-NEXT:   .long 0
96; Loc 1: Register
97; CHECK-NEXT:   .byte 1
98; CHECK-NEXT:   .byte 8
99; CHECK-NEXT:   .short {{[0-9]+}}
100; CHECK-NEXT:   .long 0
101define i64 @property_access2() nounwind ssp uwtable {
102entry:
103  %obj = alloca i64, align 8
104  %f = inttoptr i64 281474417671919 to i8*
105  %ret = call anyregcc i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 2, i32 24, i8* %f, i32 1, i64* %obj)
106  ret i64 %ret
107}
108
109; property access 3 - %obj is a frame index
110; CHECK-LABEL:  .long   .L{{.*}}-.L.property_access3
111; CHECK-NEXT:   .short  0
112; 2 locations
113; CHECK-NEXT:   .short  2
114; Loc 0: Register <-- this is the return register
115; CHECK-NEXT:   .byte 1
116; CHECK-NEXT:   .byte 8
117; CHECK-NEXT:   .short {{[0-9]+}}
118; CHECK-NEXT:   .long 0
119; Loc 1: Direct FP - 8
120; CHECK-NEXT:   .byte 2
121; CHECK-NEXT:   .byte 8
122; CHECK-NEXT:   .short 31
123; CHECK-NEXT:   .long 112
124define i64 @property_access3() nounwind ssp uwtable {
125entry:
126  %obj = alloca i64, align 8
127  %f = inttoptr i64 281474417671919 to i8*
128  %ret = call anyregcc i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 3, i32 24, i8* %f, i32 0, i64* %obj)
129  ret i64 %ret
130}
131
132; anyreg_test1
133; CHECK-LABEL:  .long   .L{{.*}}-.L.anyreg_test1
134; CHECK-NEXT:   .short  0
135; 14 locations
136; CHECK-NEXT:   .short  14
137; Loc 0: Register <-- this is the return register
138; CHECK-NEXT:   .byte 1
139; CHECK-NEXT:   .byte 8
140; CHECK-NEXT:   .short {{[0-9]+}}
141; CHECK-NEXT:   .long 0
142; Loc 1: Register
143; CHECK-NEXT:   .byte 1
144; CHECK-NEXT:   .byte 8
145; CHECK-NEXT:   .short {{[0-9]+}}
146; CHECK-NEXT:   .long 0
147; Loc 2: Register
148; CHECK-NEXT:   .byte 1
149; CHECK-NEXT:   .byte 8
150; CHECK-NEXT:   .short {{[0-9]+}}
151; CHECK-NEXT:   .long 0
152; Loc 3: Register
153; CHECK-NEXT:   .byte 1
154; CHECK-NEXT:   .byte 8
155; CHECK-NEXT:   .short {{[0-9]+}}
156; CHECK-NEXT:   .long 0
157; Loc 4: Register
158; CHECK-NEXT:   .byte 1
159; CHECK-NEXT:   .byte 8
160; CHECK-NEXT:   .short {{[0-9]+}}
161; CHECK-NEXT:   .long 0
162; Loc 5: Register
163; CHECK-NEXT:   .byte 1
164; CHECK-NEXT:   .byte 8
165; CHECK-NEXT:   .short {{[0-9]+}}
166; CHECK-NEXT:   .long 0
167; Loc 6: Register
168; CHECK-NEXT:   .byte 1
169; CHECK-NEXT:   .byte 8
170; CHECK-NEXT:   .short {{[0-9]+}}
171; CHECK-NEXT:   .long 0
172; Loc 7: Register
173; CHECK-NEXT:   .byte 1
174; CHECK-NEXT:   .byte 8
175; CHECK-NEXT:   .short {{[0-9]+}}
176; CHECK-NEXT:   .long 0
177; Loc 8: Register
178; CHECK-NEXT:   .byte 1
179; CHECK-NEXT:   .byte 8
180; CHECK-NEXT:   .short {{[0-9]+}}
181; CHECK-NEXT:   .long 0
182; Loc 9: Register
183; CHECK-NEXT:   .byte 1
184; CHECK-NEXT:   .byte 8
185; CHECK-NEXT:   .short {{[0-9]+}}
186; CHECK-NEXT:   .long 0
187; Loc 10: Register
188; CHECK-NEXT:   .byte 1
189; CHECK-NEXT:   .byte 8
190; CHECK-NEXT:   .short {{[0-9]+}}
191; CHECK-NEXT:   .long 0
192; Loc 11: Register
193; CHECK-NEXT:   .byte 1
194; CHECK-NEXT:   .byte 8
195; CHECK-NEXT:   .short {{[0-9]+}}
196; CHECK-NEXT:   .long 0
197; Loc 12: Register
198; CHECK-NEXT:   .byte 1
199; CHECK-NEXT:   .byte 8
200; CHECK-NEXT:   .short {{[0-9]+}}
201; CHECK-NEXT:   .long 0
202; Loc 13: Register
203; CHECK-NEXT:   .byte 1
204; CHECK-NEXT:   .byte 8
205; CHECK-NEXT:   .short {{[0-9]+}}
206; CHECK-NEXT:   .long 0
207define i64 @anyreg_test1(i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12, i8* %a13) nounwind ssp uwtable {
208entry:
209  %f = inttoptr i64 281474417671919 to i8*
210  %ret = call anyregcc i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 4, i32 24, i8* %f, i32 13, i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12, i8* %a13)
211  ret i64 %ret
212}
213
214; anyreg_test2
215; CHECK-LABEL:  .long   .L{{.*}}-.L.anyreg_test2
216; CHECK-NEXT:   .short  0
217; 14 locations
218; CHECK-NEXT:   .short  14
219; Loc 0: Register <-- this is the return register
220; CHECK-NEXT:   .byte 1
221; CHECK-NEXT:   .byte 8
222; CHECK-NEXT:   .short {{[0-9]+}}
223; CHECK-NEXT:   .long 0
224; Loc 1: Register
225; CHECK-NEXT:   .byte 1
226; CHECK-NEXT:   .byte 8
227; CHECK-NEXT:   .short {{[0-9]+}}
228; CHECK-NEXT:   .long 0
229; Loc 2: Register
230; CHECK-NEXT:   .byte 1
231; CHECK-NEXT:   .byte 8
232; CHECK-NEXT:   .short {{[0-9]+}}
233; CHECK-NEXT:   .long 0
234; Loc 3: Register
235; CHECK-NEXT:   .byte 1
236; CHECK-NEXT:   .byte 8
237; CHECK-NEXT:   .short {{[0-9]+}}
238; CHECK-NEXT:   .long 0
239; Loc 4: Register
240; CHECK-NEXT:   .byte 1
241; CHECK-NEXT:   .byte 8
242; CHECK-NEXT:   .short {{[0-9]+}}
243; CHECK-NEXT:   .long 0
244; Loc 5: Register
245; CHECK-NEXT:   .byte 1
246; CHECK-NEXT:   .byte 8
247; CHECK-NEXT:   .short {{[0-9]+}}
248; CHECK-NEXT:   .long 0
249; Loc 6: Register
250; CHECK-NEXT:   .byte 1
251; CHECK-NEXT:   .byte 8
252; CHECK-NEXT:   .short {{[0-9]+}}
253; CHECK-NEXT:   .long 0
254; Loc 7: Register
255; CHECK-NEXT:   .byte 1
256; CHECK-NEXT:   .byte 8
257; CHECK-NEXT:   .short {{[0-9]+}}
258; CHECK-NEXT:   .long 0
259; Loc 8: Register
260; CHECK-NEXT:   .byte 1
261; CHECK-NEXT:   .byte 8
262; CHECK-NEXT:   .short {{[0-9]+}}
263; CHECK-NEXT:   .long 0
264; Loc 9: Register
265; CHECK-NEXT:   .byte 1
266; CHECK-NEXT:   .byte 8
267; CHECK-NEXT:   .short {{[0-9]+}}
268; CHECK-NEXT:   .long 0
269; Loc 10: Register
270; CHECK-NEXT:   .byte 1
271; CHECK-NEXT:   .byte 8
272; CHECK-NEXT:   .short {{[0-9]+}}
273; CHECK-NEXT:   .long 0
274; Loc 11: Register
275; CHECK-NEXT:   .byte 1
276; CHECK-NEXT:   .byte 8
277; CHECK-NEXT:   .short {{[0-9]+}}
278; CHECK-NEXT:   .long 0
279; Loc 12: Register
280; CHECK-NEXT:   .byte 1
281; CHECK-NEXT:   .byte 8
282; CHECK-NEXT:   .short {{[0-9]+}}
283; CHECK-NEXT:   .long 0
284; Loc 13: Register
285; CHECK-NEXT:   .byte 1
286; CHECK-NEXT:   .byte 8
287; CHECK-NEXT:   .short {{[0-9]+}}
288; CHECK-NEXT:   .long 0
289define i64 @anyreg_test2(i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12, i8* %a13) nounwind ssp uwtable {
290entry:
291  %f = inttoptr i64 281474417671919 to i8*
292  %ret = call anyregcc i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 5, i32 24, i8* %f, i32 8, i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12, i8* %a13)
293  ret i64 %ret
294}
295
296; Test spilling the return value of an anyregcc call.
297;
298; <rdar://problem/15432754> [JS] Assertion: "Folded a def to a non-store!"
299;
300; CHECK-LABEL: .long .L{{.*}}-.L.patchpoint_spilldef
301; CHECK-NEXT: .short 0
302; CHECK-NEXT: .short 3
303; Loc 0: Register (some register that will be spilled to the stack)
304; CHECK-NEXT: .byte  1
305; CHECK-NEXT: .byte  8
306; CHECK-NEXT: .short {{[0-9]+}}
307; CHECK-NEXT: .long  0
308; Loc 1: Register
309; CHECK-NEXT: .byte  1
310; CHECK-NEXT: .byte  8
311; CHECK-NEXT: .short {{[0-9]+}}
312; CHECK-NEXT: .long  0
313; Loc 1: Register
314; CHECK-NEXT: .byte  1
315; CHECK-NEXT: .byte  8
316; CHECK-NEXT: .short {{[0-9]+}}
317; CHECK-NEXT: .long  0
318define i64 @patchpoint_spilldef(i64 %p1, i64 %p2, i64 %p3, i64 %p4) {
319entry:
320  %result = tail call anyregcc i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 12, i32 24, i8* inttoptr (i64 0 to i8*), i32 2, i64 %p1, i64 %p2)
321  tail call void asm sideeffect "nop", "~{r0},~{r3},~{r4},~{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11},~{r12},~{r14},~{r15},~{r16},~{r17
322},~{r18},~{r19},~{r20},~{r21},~{r22},~{r23},~{r24},~{r25},~{r26},~{r27},~{r28},~{r29},~{r30},~{r31}"() nounwind
323  ret i64 %result
324}
325
326; Test spilling the arguments of an anyregcc call.
327;
328; <rdar://problem/15487687> [JS] AnyRegCC argument ends up being spilled
329;
330; CHECK-LABEL: .long .L{{.*}}-.L.patchpoint_spillargs
331; CHECK-NEXT: .short 0
332; CHECK-NEXT: .short 5
333; Loc 0: Return a register
334; CHECK-NEXT: .byte  1
335; CHECK-NEXT: .byte  8
336; CHECK-NEXT: .short {{[0-9]+}}
337; CHECK-NEXT: .long  0
338; Loc 1: Arg0 in a Register
339; CHECK-NEXT: .byte  1
340; CHECK-NEXT: .byte  8
341; CHECK-NEXT: .short {{[0-9]+}}
342; CHECK-NEXT: .long  0
343; Loc 2: Arg1 in a Register
344; CHECK-NEXT: .byte  1
345; CHECK-NEXT: .byte  8
346; CHECK-NEXT: .short {{[0-9]+}}
347; CHECK-NEXT: .long  0
348; Loc 3: Arg2 spilled to FP -96
349; CHECK-NEXT: .byte  3
350; CHECK-NEXT: .byte  8
351; CHECK-NEXT: .short 31
352; CHECK-NEXT: .long 128
353; Loc 4: Arg3 spilled to FP - 88
354; CHECK-NEXT: .byte  3
355; CHECK-NEXT: .byte  8
356; CHECK-NEXT: .short 31
357; CHECK-NEXT: .long 136
358define i64 @patchpoint_spillargs(i64 %p1, i64 %p2, i64 %p3, i64 %p4) {
359entry:
360  tail call void asm sideeffect "nop", "~{r0},~{r3},~{r4},~{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11},~{r12},~{r14},~{r15},~{r16},~{r17
361},~{r18},~{r19},~{r20},~{r21},~{r22},~{r23},~{r24},~{r25},~{r26},~{r27},~{r28},~{r29},~{r30},~{r31}"() nounwind
362  %result = tail call anyregcc i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 13, i32 24, i8* inttoptr (i64 0 to i8*), i32 2, i64 %p1, i64 %p2, i64 %p3, i64 %p4)
363  ret i64 %result
364}
365
366declare void @llvm.experimental.patchpoint.void(i64, i32, i8*, i32, ...)
367declare i64 @llvm.experimental.patchpoint.i64(i64, i32, i8*, i32, ...)
368