1; RUN: llc < %s -mtriple=powerpc-unknown-linux-gnu -march=ppc32 -mattr=+altivec -mattr=-vsx | FileCheck %s
2; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -march=ppc64 -mattr=+altivec -mattr=-vsx -mcpu=pwr7 | FileCheck %s
3; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -march=ppc64 -mattr=+altivec -mattr=-vsx -mcpu=pwr8 | FileCheck %s -check-prefix=CHECK-LE
4; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -march=ppc64 -mattr=+altivec -mattr=+vsx -mcpu=pwr7 | FileCheck %s -check-prefix=CHECK-VSX
5; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -march=ppc64 -mattr=+altivec -mattr=+vsx -mcpu=pwr8 | FileCheck %s -check-prefix=CHECK-LE-VSX
6
7define <4 x i32> @test_v4i32(<4 x i32>* %X, <4 x i32>* %Y) {
8	%tmp = load <4 x i32>* %X		; <<4 x i32>> [#uses=1]
9	%tmp2 = load <4 x i32>* %Y		; <<4 x i32>> [#uses=1]
10	%tmp3 = mul <4 x i32> %tmp, %tmp2		; <<4 x i32>> [#uses=1]
11	ret <4 x i32> %tmp3
12}
13; CHECK-LABEL: test_v4i32:
14; CHECK: vmsumuhm
15; CHECK-NOT: mullw
16; CHECK-LE-LABEL: test_v4i32:
17; CHECK-LE: vmsumuhm
18; CHECK-LE-NOT: mullw
19; CHECK-VSX-LABEL: test_v4i32:
20; CHECK-VSX: vmsumuhm
21; CHECK-VSX-NOT: mullw
22; CHECK-LE-VSX-LABEL: test_v4i32:
23; CHECK-LE-VSX: vmsumuhm
24; CHECK-LE-VSX-NOT: mullw
25
26define <8 x i16> @test_v8i16(<8 x i16>* %X, <8 x i16>* %Y) {
27	%tmp = load <8 x i16>* %X		; <<8 x i16>> [#uses=1]
28	%tmp2 = load <8 x i16>* %Y		; <<8 x i16>> [#uses=1]
29	%tmp3 = mul <8 x i16> %tmp, %tmp2		; <<8 x i16>> [#uses=1]
30	ret <8 x i16> %tmp3
31}
32; CHECK-LABEL: test_v8i16:
33; CHECK: vmladduhm
34; CHECK-NOT: mullw
35; CHECK-LE-LABEL: test_v8i16:
36; CHECK-LE: vmladduhm
37; CHECK-LE-NOT: mullw
38; CHECK-VSX-LABEL: test_v8i16:
39; CHECK-VSX: vmladduhm
40; CHECK-VSX-NOT: mullw
41; CHECK-LE-VSX-LABEL: test_v8i16:
42; CHECK-LE-VSX: vmladduhm
43; CHECK-LE-VSX-NOT: mullw
44
45define <16 x i8> @test_v16i8(<16 x i8>* %X, <16 x i8>* %Y) {
46	%tmp = load <16 x i8>* %X		; <<16 x i8>> [#uses=1]
47	%tmp2 = load <16 x i8>* %Y		; <<16 x i8>> [#uses=1]
48	%tmp3 = mul <16 x i8> %tmp, %tmp2		; <<16 x i8>> [#uses=1]
49	ret <16 x i8> %tmp3
50}
51; CHECK-LABEL: test_v16i8:
52; CHECK: vmuloub
53; CHECK: vmuleub
54; CHECK-NOT: mullw
55; CHECK-LE-LABEL: test_v16i8:
56; CHECK-LE: vmuloub [[REG1:[0-9]+]]
57; CHECK-LE: vmuleub [[REG2:[0-9]+]]
58; CHECK-LE: vperm {{[0-9]+}}, [[REG2]], [[REG1]]
59; CHECK-LE-NOT: mullw
60; CHECK-VSX-LABEL: test_v16i8:
61; CHECK-VSX: vmuloub
62; CHECK-VSX: vmuleub
63; CHECK-VSX-NOT: mullw
64; CHECK-LE-VSX-LABEL: test_v16i8:
65; CHECK-LE-VSX: vmuloub [[REG1:[0-9]+]]
66; CHECK-LE-VSX: vmuleub [[REG2:[0-9]+]]
67; CHECK-LE-VSX: vperm {{[0-9]+}}, [[REG2]], [[REG1]]
68; CHECK-LE-VSX-NOT: mullw
69
70define <4 x float> @test_float(<4 x float>* %X, <4 x float>* %Y) {
71	%tmp = load <4 x float>* %X
72	%tmp2 = load <4 x float>* %Y
73	%tmp3 = fmul <4 x float> %tmp, %tmp2
74	ret <4 x float> %tmp3
75}
76; Check the creation of a negative zero float vector by creating a vector of
77; all bits set and shifting it 31 bits to left, resulting a an vector of
78; 4 x 0x80000000 (-0.0 as float).
79; CHECK-LABEL: test_float:
80; CHECK: vspltisw [[ZNEG:[0-9]+]], -1
81; CHECK: vslw     {{[0-9]+}}, [[ZNEG]], [[ZNEG]]
82; CHECK: vmaddfp
83; CHECK-LE-LABEL: test_float:
84; CHECK-LE: vspltisw [[ZNEG:[0-9]+]], -1
85; CHECK-LE: vslw     {{[0-9]+}}, [[ZNEG]], [[ZNEG]]
86; CHECK-LE: vmaddfp
87; CHECK-VSX-LABEL: test_float:
88; CHECK-VSX: xvmulsp
89; CHECK-LE-VSX-LABEL: test_float:
90; CHECK-LE-VSX: xvmulsp
91