1; RUN: llc < %s -march=r600 -mcpu=r600 | FileCheck %s
2; RUN: llc < %s -march=r600 -mcpu=rs880 | FileCheck %s
3; RUN: llc < %s -march=r600 -mcpu=rv670 | FileCheck %s
4
5; R600 supports 8 fetches in a clause
6; CHECK: @fetch_limits_r600
7; CHECK: Fetch clause
8; CHECK: Fetch clause
9
10define void @fetch_limits_r600() #0 {
11entry:
12  %0 = load <4 x float> addrspace(8)* null
13  %1 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
14  %2 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
15  %3 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3)
16  %4 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 4)
17  %5 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 5)
18  %6 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 6)
19  %7 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 7)
20  %8 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 8)
21  %res0 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %0, i32 0, i32 0, i32 1)
22  %res1 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %1, i32 0, i32 0, i32 1)
23  %res2 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %2, i32 0, i32 0, i32 1)
24  %res3 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %3, i32 0, i32 0, i32 1)
25  %res4 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %4, i32 0, i32 0, i32 1)
26  %res5 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %5, i32 0, i32 0, i32 1)
27  %res6 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %6, i32 0, i32 0, i32 1)
28  %res7 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %7, i32 0, i32 0, i32 1)
29  %res8 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %8, i32 0, i32 0, i32 1)
30  %a = fadd <4 x float> %res0, %res1
31  %b = fadd <4 x float> %res2, %res3
32  %c = fadd <4 x float> %res4, %res5
33  %d = fadd <4 x float> %res6, %res7
34  %e = fadd <4 x float> %res8, %a
35
36  %bc = fadd <4 x float> %b, %c
37  %de = fadd <4 x float> %d, %e
38
39  %bcde = fadd <4 x float> %bc, %de
40
41  call void @llvm.R600.store.swizzle(<4 x float> %bcde, i32 0, i32 1)
42  ret void
43}
44
45attributes #0 = { "ShaderType"="0" } ; Pixel Shader
46
47declare <4 x float> @llvm.AMDGPU.tex(<4 x float>, i32, i32, i32) readnone
48declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)
49