1; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=R600-CHECK
2; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck %s --check-prefix=SI-CHECK
3
4; R600-CHECK-LABEL: @fneg
5; R600-CHECK: -PV
6; SI-CHECK-LABEL: @fneg
7; SI-CHECK: V_ADD_F32_e64 v{{[0-9]}}, s{{[0-9]}}, 0, 0, 0, 0, 1
8define void @fneg(float addrspace(1)* %out, float %in) {
9entry:
10  %0 = fsub float -0.000000e+00, %in
11  store float %0, float addrspace(1)* %out
12  ret void
13}
14
15; R600-CHECK-LABEL: @fneg_v2
16; R600-CHECK: -PV
17; R600-CHECK: -PV
18; SI-CHECK-LABEL: @fneg_v2
19; SI-CHECK: V_ADD_F32_e64 v{{[0-9]}}, s{{[0-9]}}, 0, 0, 0, 0, 1
20; SI-CHECK: V_ADD_F32_e64 v{{[0-9]}}, s{{[0-9]}}, 0, 0, 0, 0, 1
21define void @fneg_v2(<2 x float> addrspace(1)* nocapture %out, <2 x float> %in) {
22entry:
23  %0 = fsub <2 x float> <float -0.000000e+00, float -0.000000e+00>, %in
24  store <2 x float> %0, <2 x float> addrspace(1)* %out
25  ret void
26}
27
28; R600-CHECK-LABEL: @fneg_v4
29; R600-CHECK: -PV
30; R600-CHECK: -T
31; R600-CHECK: -PV
32; R600-CHECK: -PV
33; SI-CHECK-LABEL: @fneg_v4
34; SI-CHECK: V_ADD_F32_e64 v{{[0-9]}}, s{{[0-9]}}, 0, 0, 0, 0, 1
35; SI-CHECK: V_ADD_F32_e64 v{{[0-9]}}, s{{[0-9]}}, 0, 0, 0, 0, 1
36; SI-CHECK: V_ADD_F32_e64 v{{[0-9]}}, s{{[0-9]}}, 0, 0, 0, 0, 1
37; SI-CHECK: V_ADD_F32_e64 v{{[0-9]}}, s{{[0-9]}}, 0, 0, 0, 0, 1
38define void @fneg_v4(<4 x float> addrspace(1)* nocapture %out, <4 x float> %in) {
39entry:
40  %0 = fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %in
41  store <4 x float> %0, <4 x float> addrspace(1)* %out
42  ret void
43}
44
45; DAGCombiner will transform:
46; (fneg (f32 bitcast (i32 a))) => (f32 bitcast (xor (i32 a), 0x80000000))
47; unless the target returns true for isNegFree()
48
49; R600-CHECK-LABEL: @fneg_free
50; R600-CHECK-NOT: XOR
51; R600-CHECK: -KC0[2].Z
52; SI-CHECK-LABEL: @fneg_free
53; XXX: We could use V_ADD_F32_e64 with the negate bit here instead.
54; SI-CHECK: V_SUB_F32_e64 v{{[0-9]}}, 0.000000e+00, s{{[0-9]}}, 0, 0, 0, 0
55define void @fneg_free(float addrspace(1)* %out, i32 %in) {
56entry:
57  %0 = bitcast i32 %in to float
58  %1 = fsub float 0.0, %0
59  store float %1, float addrspace(1)* %out
60  ret void
61}
62