1; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=EG-CHECK
2; RUN: llc < %s -march=r600 -mcpu=cayman | FileCheck %s --check-prefix=EG-CHECK
3; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck %s --check-prefix=SI-CHECK
4
5; EG-CHECK-LABEL: @i8_arg
6; EG-CHECK: MOV {{[ *]*}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z
7; SI-CHECK-LABEL: @i8_arg
8; SI-CHECK: BUFFER_LOAD_UBYTE
9
10define void @i8_arg(i32 addrspace(1)* nocapture %out, i8 %in) nounwind {
11entry:
12  %0 = zext i8 %in to i32
13  store i32 %0, i32 addrspace(1)* %out, align 4
14  ret void
15}
16
17; EG-CHECK-LABEL: @i8_zext_arg
18; EG-CHECK: MOV {{[ *]*}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z
19; SI-CHECK-LABEL: @i8_zext_arg
20; SI-CHECK: S_LOAD_DWORD s{{[0-9]}}, s[0:1], 11
21
22define void @i8_zext_arg(i32 addrspace(1)* nocapture %out, i8 zeroext %in) nounwind {
23entry:
24  %0 = zext i8 %in to i32
25  store i32 %0, i32 addrspace(1)* %out, align 4
26  ret void
27}
28
29; EG-CHECK-LABEL: @i8_sext_arg
30; EG-CHECK: MOV {{[ *]*}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z
31; SI-CHECK-LABEL: @i8_sext_arg
32; SI-CHECK: S_LOAD_DWORD s{{[0-9]}}, s[0:1], 11
33
34define void @i8_sext_arg(i32 addrspace(1)* nocapture %out, i8 signext %in) nounwind {
35entry:
36  %0 = sext i8 %in to i32
37  store i32 %0, i32 addrspace(1)* %out, align 4
38  ret void
39}
40
41; EG-CHECK-LABEL: @i16_arg
42; EG-CHECK: MOV {{[ *]*}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z
43; SI-CHECK-LABEL: @i16_arg
44; SI-CHECK: BUFFER_LOAD_USHORT
45
46define void @i16_arg(i32 addrspace(1)* nocapture %out, i16 %in) nounwind {
47entry:
48  %0 = zext i16 %in to i32
49  store i32 %0, i32 addrspace(1)* %out, align 4
50  ret void
51}
52
53; EG-CHECK-LABEL: @i16_zext_arg
54; EG-CHECK: MOV {{[ *]*}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z
55; SI-CHECK-LABEL: @i16_zext_arg
56; SI-CHECK: S_LOAD_DWORD s{{[0-9]}}, s[0:1], 11
57
58define void @i16_zext_arg(i32 addrspace(1)* nocapture %out, i16 zeroext %in) nounwind {
59entry:
60  %0 = zext i16 %in to i32
61  store i32 %0, i32 addrspace(1)* %out, align 4
62  ret void
63}
64
65; EG-CHECK-LABEL: @i16_sext_arg
66; EG-CHECK: MOV {{[ *]*}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z
67; SI-CHECK-LABEL: @i16_sext_arg
68; SI-CHECK: S_LOAD_DWORD s{{[0-9]}}, s[0:1], 11
69
70define void @i16_sext_arg(i32 addrspace(1)* nocapture %out, i16 signext %in) nounwind {
71entry:
72  %0 = sext i16 %in to i32
73  store i32 %0, i32 addrspace(1)* %out, align 4
74  ret void
75}
76
77; EG-CHECK-LABEL: @i32_arg
78; EG-CHECK: T{{[0-9]\.[XYZW]}}, KC0[2].Z
79; SI-CHECK-LABEL: @i32_arg
80; S_LOAD_DWORD s{{[0-9]}}, s[0:1], 11
81define void @i32_arg(i32 addrspace(1)* nocapture %out, i32 %in) nounwind {
82entry:
83  store i32 %in, i32 addrspace(1)* %out, align 4
84  ret void
85}
86
87; EG-CHECK-LABEL: @f32_arg
88; EG-CHECK: T{{[0-9]\.[XYZW]}}, KC0[2].Z
89; SI-CHECK-LABEL: @f32_arg
90; S_LOAD_DWORD s{{[0-9]}}, s[0:1], 11
91define void @f32_arg(float addrspace(1)* nocapture %out, float %in) nounwind {
92entry:
93  store float %in, float addrspace(1)* %out, align 4
94  ret void
95}
96
97; EG-CHECK-LABEL: @v2i8_arg
98; EG-CHECK: VTX_READ_8
99; EG-CHECK: VTX_READ_8
100; SI-CHECK-LABEL: @v2i8_arg
101; SI-CHECK: BUFFER_LOAD_UBYTE
102; SI-CHECK: BUFFER_LOAD_UBYTE
103define void @v2i8_arg(<2 x i8> addrspace(1)* %out, <2 x i8> %in) {
104entry:
105  store <2 x i8> %in, <2 x i8> addrspace(1)* %out
106  ret void
107}
108
109; EG-CHECK-LABEL: @v2i16_arg
110; EG-CHECK: VTX_READ_16
111; EG-CHECK: VTX_READ_16
112; SI-CHECK-LABEL: @v2i16_arg
113; SI-CHECK-DAG: BUFFER_LOAD_USHORT
114; SI-CHECK-DAG: BUFFER_LOAD_USHORT
115define void @v2i16_arg(<2 x i16> addrspace(1)* %out, <2 x i16> %in) {
116entry:
117  store <2 x i16> %in, <2 x i16> addrspace(1)* %out
118  ret void
119}
120
121; EG-CHECK-LABEL: @v2i32_arg
122; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].X
123; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[2].W
124; SI-CHECK-LABEL: @v2i32_arg
125; SI-CHECK: S_LOAD_DWORDX2 s{{\[[0-9]:[0-9]\]}}, s[0:1], 11
126define void @v2i32_arg(<2 x i32> addrspace(1)* nocapture %out, <2 x i32> %in) nounwind {
127entry:
128  store <2 x i32> %in, <2 x i32> addrspace(1)* %out, align 4
129  ret void
130}
131
132; EG-CHECK-LABEL: @v2f32_arg
133; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].X
134; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[2].W
135; SI-CHECK-LABEL: @v2f32_arg
136; SI-CHECK: S_LOAD_DWORDX2 s{{\[[0-9]:[0-9]\]}}, s[0:1], 11
137define void @v2f32_arg(<2 x float> addrspace(1)* nocapture %out, <2 x float> %in) nounwind {
138entry:
139  store <2 x float> %in, <2 x float> addrspace(1)* %out, align 4
140  ret void
141}
142
143; EG-CHECK-LABEL: @v3i8_arg
144; VTX_READ_8 T{{[0-9]}}.X, T{{[0-9]}}.X, 40
145; VTX_READ_8 T{{[0-9]}}.X, T{{[0-9]}}.X, 41
146; VTX_READ_8 T{{[0-9]}}.X, T{{[0-9]}}.X, 42
147; SI-CHECK-LABEL: @v3i8_arg
148define void @v3i8_arg(<3 x i8> addrspace(1)* nocapture %out, <3 x i8> %in) nounwind {
149entry:
150  store <3 x i8> %in, <3 x i8> addrspace(1)* %out, align 4
151  ret void
152}
153
154; EG-CHECK-LABEL: @v3i16_arg
155; VTX_READ_16 T{{[0-9]}}.X, T{{[0-9]}}.X, 44
156; VTX_READ_16 T{{[0-9]}}.X, T{{[0-9]}}.X, 46
157; VTX_READ_16 T{{[0-9]}}.X, T{{[0-9]}}.X, 48
158; SI-CHECK-LABEL: @v3i16_arg
159define void @v3i16_arg(<3 x i16> addrspace(1)* nocapture %out, <3 x i16> %in) nounwind {
160entry:
161  store <3 x i16> %in, <3 x i16> addrspace(1)* %out, align 4
162  ret void
163}
164; EG-CHECK-LABEL: @v3i32_arg
165; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].Y
166; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].Z
167; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].W
168; SI-CHECK-LABEL: @v3i32_arg
169; SI-CHECK: S_LOAD_DWORDX4 s{{\[[0-9]:[0-9]+\]}}, s[0:1], 13
170define void @v3i32_arg(<3 x i32> addrspace(1)* nocapture %out, <3 x i32> %in) nounwind {
171entry:
172  store <3 x i32> %in, <3 x i32> addrspace(1)* %out, align 4
173  ret void
174}
175
176; EG-CHECK-LABEL: @v3f32_arg
177; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].Y
178; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].Z
179; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].W
180; SI-CHECK-LABEL: @v3f32_arg
181; SI-CHECK: S_LOAD_DWORDX4 s{{\[[0-9]:[0-9]+\]}}, s[0:1], 13
182define void @v3f32_arg(<3 x float> addrspace(1)* nocapture %out, <3 x float> %in) nounwind {
183entry:
184  store <3 x float> %in, <3 x float> addrspace(1)* %out, align 4
185  ret void
186}
187
188; EG-CHECK-LABEL: @v4i8_arg
189; EG-CHECK: VTX_READ_8
190; EG-CHECK: VTX_READ_8
191; EG-CHECK: VTX_READ_8
192; EG-CHECK: VTX_READ_8
193; SI-CHECK-LABEL: @v4i8_arg
194; SI-CHECK: BUFFER_LOAD_UBYTE
195; SI-CHECK: BUFFER_LOAD_UBYTE
196; SI-CHECK: BUFFER_LOAD_UBYTE
197; SI-CHECK: BUFFER_LOAD_UBYTE
198define void @v4i8_arg(<4 x i8> addrspace(1)* %out, <4 x i8> %in) {
199entry:
200  store <4 x i8> %in, <4 x i8> addrspace(1)* %out
201  ret void
202}
203
204; EG-CHECK-LABEL: @v4i16_arg
205; EG-CHECK: VTX_READ_16
206; EG-CHECK: VTX_READ_16
207; EG-CHECK: VTX_READ_16
208; EG-CHECK: VTX_READ_16
209; SI-CHECK-LABEL: @v4i16_arg
210; SI-CHECK: BUFFER_LOAD_USHORT
211; SI-CHECK: BUFFER_LOAD_USHORT
212; SI-CHECK: BUFFER_LOAD_USHORT
213; SI-CHECK: BUFFER_LOAD_USHORT
214define void @v4i16_arg(<4 x i16> addrspace(1)* %out, <4 x i16> %in) {
215entry:
216  store <4 x i16> %in, <4 x i16> addrspace(1)* %out
217  ret void
218}
219
220; EG-CHECK-LABEL: @v4i32_arg
221; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].Y
222; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].Z
223; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].W
224; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[4].X
225; SI-CHECK-LABEL: @v4i32_arg
226; SI-CHECK: S_LOAD_DWORDX4 s{{\[[0-9]:[0-9]\]}}, s[0:1], 13
227define void @v4i32_arg(<4 x i32> addrspace(1)* nocapture %out, <4 x i32> %in) nounwind {
228entry:
229  store <4 x i32> %in, <4 x i32> addrspace(1)* %out, align 4
230  ret void
231}
232
233; EG-CHECK-LABEL: @v4f32_arg
234; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].Y
235; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].Z
236; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].W
237; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[4].X
238; SI-CHECK-LABEL: @v4f32_arg
239; SI-CHECK: S_LOAD_DWORDX4 s{{\[[0-9]:[0-9]\]}}, s[0:1], 13
240define void @v4f32_arg(<4 x float> addrspace(1)* nocapture %out, <4 x float> %in) nounwind {
241entry:
242  store <4 x float> %in, <4 x float> addrspace(1)* %out, align 4
243  ret void
244}
245
246; EG-CHECK-LABEL: @v8i8_arg
247; EG-CHECK: VTX_READ_8
248; EG-CHECK: VTX_READ_8
249; EG-CHECK: VTX_READ_8
250; EG-CHECK: VTX_READ_8
251; EG-CHECK: VTX_READ_8
252; EG-CHECK: VTX_READ_8
253; EG-CHECK: VTX_READ_8
254; EG-CHECK: VTX_READ_8
255; SI-CHECK-LABEL: @v8i8_arg
256; SI-CHECK: BUFFER_LOAD_UBYTE
257; SI-CHECK: BUFFER_LOAD_UBYTE
258; SI-CHECK: BUFFER_LOAD_UBYTE
259; SI-CHECK: BUFFER_LOAD_UBYTE
260; SI-CHECK: BUFFER_LOAD_UBYTE
261; SI-CHECK: BUFFER_LOAD_UBYTE
262; SI-CHECK: BUFFER_LOAD_UBYTE
263define void @v8i8_arg(<8 x i8> addrspace(1)* %out, <8 x i8> %in) {
264entry:
265  store <8 x i8> %in, <8 x i8> addrspace(1)* %out
266  ret void
267}
268
269; EG-CHECK-LABEL: @v8i16_arg
270; EG-CHECK: VTX_READ_16
271; EG-CHECK: VTX_READ_16
272; EG-CHECK: VTX_READ_16
273; EG-CHECK: VTX_READ_16
274; EG-CHECK: VTX_READ_16
275; EG-CHECK: VTX_READ_16
276; EG-CHECK: VTX_READ_16
277; EG-CHECK: VTX_READ_16
278; SI-CHECK-LABEL: @v8i16_arg
279; SI-CHECK: BUFFER_LOAD_USHORT
280; SI-CHECK: BUFFER_LOAD_USHORT
281; SI-CHECK: BUFFER_LOAD_USHORT
282; SI-CHECK: BUFFER_LOAD_USHORT
283; SI-CHECK: BUFFER_LOAD_USHORT
284; SI-CHECK: BUFFER_LOAD_USHORT
285; SI-CHECK: BUFFER_LOAD_USHORT
286; SI-CHECK: BUFFER_LOAD_USHORT
287define void @v8i16_arg(<8 x i16> addrspace(1)* %out, <8 x i16> %in) {
288entry:
289  store <8 x i16> %in, <8 x i16> addrspace(1)* %out
290  ret void
291}
292
293; EG-CHECK-LABEL: @v8i32_arg
294; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[4].Y
295; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[4].Z
296; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[4].W
297; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[5].X
298; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[5].Y
299; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[5].Z
300; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[5].W
301; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[6].X
302; SI-CHECK-LABEL: @v8i32_arg
303; SI-CHECK: S_LOAD_DWORDX8 s{{\[[0-9]:[0-9]+\]}}, s[0:1], 17
304define void @v8i32_arg(<8 x i32> addrspace(1)* nocapture %out, <8 x i32> %in) nounwind {
305entry:
306  store <8 x i32> %in, <8 x i32> addrspace(1)* %out, align 4
307  ret void
308}
309
310; EG-CHECK-LABEL: @v8f32_arg
311; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[4].Y
312; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[4].Z
313; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[4].W
314; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[5].X
315; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[5].Y
316; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[5].Z
317; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[5].W
318; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[6].X
319; SI-CHECK-LABEL: @v8f32_arg
320; SI-CHECK: S_LOAD_DWORDX8 s{{\[[0-9]:[0-9]+\]}}, s[0:1], 17
321define void @v8f32_arg(<8 x float> addrspace(1)* nocapture %out, <8 x float> %in) nounwind {
322entry:
323  store <8 x float> %in, <8 x float> addrspace(1)* %out, align 4
324  ret void
325}
326
327; EG-CHECK-LABEL: @v16i8_arg
328; EG-CHECK: VTX_READ_8
329; EG-CHECK: VTX_READ_8
330; EG-CHECK: VTX_READ_8
331; EG-CHECK: VTX_READ_8
332; EG-CHECK: VTX_READ_8
333; EG-CHECK: VTX_READ_8
334; EG-CHECK: VTX_READ_8
335; EG-CHECK: VTX_READ_8
336; EG-CHECK: VTX_READ_8
337; EG-CHECK: VTX_READ_8
338; EG-CHECK: VTX_READ_8
339; EG-CHECK: VTX_READ_8
340; EG-CHECK: VTX_READ_8
341; EG-CHECK: VTX_READ_8
342; EG-CHECK: VTX_READ_8
343; EG-CHECK: VTX_READ_8
344; SI-CHECK-LABEL: @v16i8_arg
345; SI-CHECK: BUFFER_LOAD_UBYTE
346; SI-CHECK: BUFFER_LOAD_UBYTE
347; SI-CHECK: BUFFER_LOAD_UBYTE
348; SI-CHECK: BUFFER_LOAD_UBYTE
349; SI-CHECK: BUFFER_LOAD_UBYTE
350; SI-CHECK: BUFFER_LOAD_UBYTE
351; SI-CHECK: BUFFER_LOAD_UBYTE
352; SI-CHECK: BUFFER_LOAD_UBYTE
353; SI-CHECK: BUFFER_LOAD_UBYTE
354; SI-CHECK: BUFFER_LOAD_UBYTE
355; SI-CHECK: BUFFER_LOAD_UBYTE
356; SI-CHECK: BUFFER_LOAD_UBYTE
357; SI-CHECK: BUFFER_LOAD_UBYTE
358; SI-CHECK: BUFFER_LOAD_UBYTE
359; SI-CHECK: BUFFER_LOAD_UBYTE
360; SI-CHECK: BUFFER_LOAD_UBYTE
361define void @v16i8_arg(<16 x i8> addrspace(1)* %out, <16 x i8> %in) {
362entry:
363  store <16 x i8> %in, <16 x i8> addrspace(1)* %out
364  ret void
365}
366
367; EG-CHECK-LABEL: @v16i16_arg
368; EG-CHECK: VTX_READ_16
369; EG-CHECK: VTX_READ_16
370; EG-CHECK: VTX_READ_16
371; EG-CHECK: VTX_READ_16
372; EG-CHECK: VTX_READ_16
373; EG-CHECK: VTX_READ_16
374; EG-CHECK: VTX_READ_16
375; EG-CHECK: VTX_READ_16
376; EG-CHECK: VTX_READ_16
377; EG-CHECK: VTX_READ_16
378; EG-CHECK: VTX_READ_16
379; EG-CHECK: VTX_READ_16
380; EG-CHECK: VTX_READ_16
381; EG-CHECK: VTX_READ_16
382; EG-CHECK: VTX_READ_16
383; EG-CHECK: VTX_READ_16
384; SI-CHECK-LABEL: @v16i16_arg
385; SI-CHECK: BUFFER_LOAD_USHORT
386; SI-CHECK: BUFFER_LOAD_USHORT
387; SI-CHECK: BUFFER_LOAD_USHORT
388; SI-CHECK: BUFFER_LOAD_USHORT
389; SI-CHECK: BUFFER_LOAD_USHORT
390; SI-CHECK: BUFFER_LOAD_USHORT
391; SI-CHECK: BUFFER_LOAD_USHORT
392; SI-CHECK: BUFFER_LOAD_USHORT
393; SI-CHECK: BUFFER_LOAD_USHORT
394; SI-CHECK: BUFFER_LOAD_USHORT
395; SI-CHECK: BUFFER_LOAD_USHORT
396; SI-CHECK: BUFFER_LOAD_USHORT
397; SI-CHECK: BUFFER_LOAD_USHORT
398; SI-CHECK: BUFFER_LOAD_USHORT
399; SI-CHECK: BUFFER_LOAD_USHORT
400; SI-CHECK: BUFFER_LOAD_USHORT
401define void @v16i16_arg(<16 x i16> addrspace(1)* %out, <16 x i16> %in) {
402entry:
403  store <16 x i16> %in, <16 x i16> addrspace(1)* %out
404  ret void
405}
406
407; EG-CHECK-LABEL: @v16i32_arg
408; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[6].Y
409; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[6].Z
410; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[6].W
411; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[7].X
412; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[7].Y
413; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[7].Z
414; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[7].W
415; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[8].X
416; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[8].Y
417; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[8].Z
418; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[8].W
419; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[9].X
420; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[9].Y
421; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[9].Z
422; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[9].W
423; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[10].X
424; SI-CHECK-LABEL: @v16i32_arg
425; SI-CHECK: S_LOAD_DWORDX16 s{{\[[0-9]:[0-9]+\]}}, s[0:1], 25
426define void @v16i32_arg(<16 x i32> addrspace(1)* nocapture %out, <16 x i32> %in) nounwind {
427entry:
428  store <16 x i32> %in, <16 x i32> addrspace(1)* %out, align 4
429  ret void
430}
431
432; EG-CHECK-LABEL: @v16f32_arg
433; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[6].Y
434; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[6].Z
435; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[6].W
436; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[7].X
437; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[7].Y
438; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[7].Z
439; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[7].W
440; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[8].X
441; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[8].Y
442; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[8].Z
443; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[8].W
444; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[9].X
445; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[9].Y
446; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[9].Z
447; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[9].W
448; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[10].X
449; SI-CHECK-LABEL: @v16f32_arg
450; SI-CHECK: S_LOAD_DWORDX16 s{{\[[0-9]:[0-9]+\]}}, s[0:1], 25
451define void @v16f32_arg(<16 x float> addrspace(1)* nocapture %out, <16 x float> %in) nounwind {
452entry:
453  store <16 x float> %in, <16 x float> addrspace(1)* %out, align 4
454  ret void
455}
456