1; RUN: llc < %s -march=r600 -mcpu=SI  | FileCheck %s
2
3; This test checks that no VGPR to SGPR copies are created by the register
4; allocator.
5; CHECK-LABEL: @phi1
6; CHECK: S_BUFFER_LOAD_DWORD [[DST:s[0-9]]], {{s\[[0-9]+:[0-9]+\]}}, 0
7; CHECK: V_MOV_B32_e32 v{{[0-9]}}, [[DST]]
8
9define void @phi1(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
10main_body:
11  %20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
12  %21 = load <16 x i8> addrspace(2)* %20, !tbaa !1
13  %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 0)
14  %23 = call float @llvm.SI.load.const(<16 x i8> %21, i32 16)
15  %24 = call float @llvm.SI.load.const(<16 x i8> %21, i32 32)
16  %25 = fptosi float %23 to i32
17  %26 = icmp ne i32 %25, 0
18  br i1 %26, label %ENDIF, label %ELSE
19
20ELSE:                                             ; preds = %main_body
21  %27 = fsub float -0.000000e+00, %22
22  br label %ENDIF
23
24ENDIF:                                            ; preds = %main_body, %ELSE
25  %temp.0 = phi float [ %27, %ELSE ], [ %22, %main_body ]
26  %28 = fadd float %temp.0, %24
27  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %28, float %28, float 0.000000e+00, float 1.000000e+00)
28  ret void
29}
30
31; Make sure this program doesn't crash
32; CHECK-LABEL: @phi2
33define void @phi2(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
34main_body:
35  %20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
36  %21 = load <16 x i8> addrspace(2)* %20, !tbaa !1
37  %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 16)
38  %23 = call float @llvm.SI.load.const(<16 x i8> %21, i32 32)
39  %24 = call float @llvm.SI.load.const(<16 x i8> %21, i32 36)
40  %25 = call float @llvm.SI.load.const(<16 x i8> %21, i32 40)
41  %26 = call float @llvm.SI.load.const(<16 x i8> %21, i32 48)
42  %27 = call float @llvm.SI.load.const(<16 x i8> %21, i32 52)
43  %28 = call float @llvm.SI.load.const(<16 x i8> %21, i32 56)
44  %29 = call float @llvm.SI.load.const(<16 x i8> %21, i32 64)
45  %30 = call float @llvm.SI.load.const(<16 x i8> %21, i32 68)
46  %31 = call float @llvm.SI.load.const(<16 x i8> %21, i32 72)
47  %32 = call float @llvm.SI.load.const(<16 x i8> %21, i32 76)
48  %33 = call float @llvm.SI.load.const(<16 x i8> %21, i32 80)
49  %34 = call float @llvm.SI.load.const(<16 x i8> %21, i32 84)
50  %35 = call float @llvm.SI.load.const(<16 x i8> %21, i32 88)
51  %36 = call float @llvm.SI.load.const(<16 x i8> %21, i32 92)
52  %37 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
53  %38 = load <32 x i8> addrspace(2)* %37, !tbaa !1
54  %39 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
55  %40 = load <16 x i8> addrspace(2)* %39, !tbaa !1
56  %41 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
57  %42 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
58  %43 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %3, <2 x i32> %5)
59  %44 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %3, <2 x i32> %5)
60  %45 = call float @llvm.SI.fs.interp(i32 2, i32 1, i32 %3, <2 x i32> %5)
61  %46 = bitcast float %41 to i32
62  %47 = bitcast float %42 to i32
63  %48 = insertelement <2 x i32> undef, i32 %46, i32 0
64  %49 = insertelement <2 x i32> %48, i32 %47, i32 1
65  %50 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %49, <32 x i8> %38, <16 x i8> %40, i32 2)
66  %51 = extractelement <4 x float> %50, i32 2
67  %52 = call float @fabs(float %51)
68  %53 = fmul float %43, %43
69  %54 = fmul float %44, %44
70  %55 = fadd float %54, %53
71  %56 = fmul float %45, %45
72  %57 = fadd float %55, %56
73  %58 = call float @llvm.AMDGPU.rsq(float %57)
74  %59 = fmul float %43, %58
75  %60 = fmul float %44, %58
76  %61 = fmul float %45, %58
77  %62 = fmul float %59, %23
78  %63 = fmul float %60, %24
79  %64 = fadd float %63, %62
80  %65 = fmul float %61, %25
81  %66 = fadd float %64, %65
82  %67 = fsub float -0.000000e+00, %26
83  %68 = fmul float %66, %52
84  %69 = fadd float %68, %67
85  %70 = fmul float %27, %69
86  %71 = fmul float %28, %69
87  %72 = call float @fabs(float %70)
88  %73 = fcmp olt float 0x3EE4F8B580000000, %72
89  %74 = sext i1 %73 to i32
90  %75 = bitcast i32 %74 to float
91  %76 = bitcast float %75 to i32
92  %77 = icmp ne i32 %76, 0
93  br i1 %77, label %IF, label %ENDIF
94
95IF:                                               ; preds = %main_body
96  %78 = fsub float -0.000000e+00, %70
97  %79 = call float @llvm.AMDIL.exp.(float %78)
98  %80 = fsub float -0.000000e+00, %79
99  %81 = fadd float 1.000000e+00, %80
100  %82 = fdiv float 1.000000e+00, %70
101  %83 = fmul float %81, %82
102  %84 = fmul float %32, %83
103  br label %ENDIF
104
105ENDIF:                                            ; preds = %main_body, %IF
106  %temp4.0 = phi float [ %84, %IF ], [ %32, %main_body ]
107  %85 = call float @fabs(float %71)
108  %86 = fcmp olt float 0x3EE4F8B580000000, %85
109  %87 = sext i1 %86 to i32
110  %88 = bitcast i32 %87 to float
111  %89 = bitcast float %88 to i32
112  %90 = icmp ne i32 %89, 0
113  br i1 %90, label %IF25, label %ENDIF24
114
115IF25:                                             ; preds = %ENDIF
116  %91 = fsub float -0.000000e+00, %71
117  %92 = call float @llvm.AMDIL.exp.(float %91)
118  %93 = fsub float -0.000000e+00, %92
119  %94 = fadd float 1.000000e+00, %93
120  %95 = fdiv float 1.000000e+00, %71
121  %96 = fmul float %94, %95
122  %97 = fmul float %36, %96
123  br label %ENDIF24
124
125ENDIF24:                                          ; preds = %ENDIF, %IF25
126  %temp8.0 = phi float [ %97, %IF25 ], [ %36, %ENDIF ]
127  %98 = fmul float %29, %temp4.0
128  %99 = fmul float %30, %temp4.0
129  %100 = fmul float %31, %temp4.0
130  %101 = fmul float %33, %temp8.0
131  %102 = fadd float %101, %98
132  %103 = fmul float %34, %temp8.0
133  %104 = fadd float %103, %99
134  %105 = fmul float %35, %temp8.0
135  %106 = fadd float %105, %100
136  %107 = call float @llvm.pow.f32(float %52, float %22)
137  %108 = fsub float -0.000000e+00, %102
138  %109 = fmul float %108, %107
139  %110 = fsub float -0.000000e+00, %104
140  %111 = fmul float %110, %107
141  %112 = fsub float -0.000000e+00, %106
142  %113 = fmul float %112, %107
143  %114 = call i32 @llvm.SI.packf16(float %109, float %111)
144  %115 = bitcast i32 %114 to float
145  %116 = call i32 @llvm.SI.packf16(float %113, float 1.000000e+00)
146  %117 = bitcast i32 %116 to float
147  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %115, float %117, float %115, float %117)
148  ret void
149}
150
151; We just want ot make sure the program doesn't crash
152; CHECK-LABEL: @loop
153
154define void @loop(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
155main_body:
156  %20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
157  %21 = load <16 x i8> addrspace(2)* %20, !tbaa !1
158  %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 0)
159  %23 = call float @llvm.SI.load.const(<16 x i8> %21, i32 4)
160  %24 = call float @llvm.SI.load.const(<16 x i8> %21, i32 8)
161  %25 = call float @llvm.SI.load.const(<16 x i8> %21, i32 12)
162  %26 = fptosi float %25 to i32
163  %27 = bitcast i32 %26 to float
164  %28 = bitcast float %27 to i32
165  br label %LOOP
166
167LOOP:                                             ; preds = %ENDIF, %main_body
168  %temp4.0 = phi float [ %22, %main_body ], [ %temp5.0, %ENDIF ]
169  %temp5.0 = phi float [ %23, %main_body ], [ %temp6.0, %ENDIF ]
170  %temp6.0 = phi float [ %24, %main_body ], [ %temp4.0, %ENDIF ]
171  %temp8.0 = phi float [ 0.000000e+00, %main_body ], [ %37, %ENDIF ]
172  %29 = bitcast float %temp8.0 to i32
173  %30 = icmp sge i32 %29, %28
174  %31 = sext i1 %30 to i32
175  %32 = bitcast i32 %31 to float
176  %33 = bitcast float %32 to i32
177  %34 = icmp ne i32 %33, 0
178  br i1 %34, label %IF, label %ENDIF
179
180IF:                                               ; preds = %LOOP
181  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %temp4.0, float %temp5.0, float %temp6.0, float 1.000000e+00)
182  ret void
183
184ENDIF:                                            ; preds = %LOOP
185  %35 = bitcast float %temp8.0 to i32
186  %36 = add i32 %35, 1
187  %37 = bitcast i32 %36 to float
188  br label %LOOP
189}
190
191; Function Attrs: nounwind readnone
192declare float @llvm.SI.load.const(<16 x i8>, i32) #1
193
194; Function Attrs: readonly
195declare float @fabs(float) #2
196
197declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
198
199attributes #0 = { "ShaderType"="0" }
200attributes #1 = { nounwind readnone }
201attributes #2 = { readonly }
202attributes #3 = { readnone }
203attributes #4 = { nounwind readonly }
204
205!0 = metadata !{metadata !"const", null}
206!1 = metadata !{metadata !0, metadata !0, i64 0, i32 1}
207
208; Function Attrs: nounwind readnone
209declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
210
211; Function Attrs: nounwind readnone
212declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1
213
214; Function Attrs: readnone
215declare float @llvm.AMDGPU.rsq(float) #3
216
217; Function Attrs: readnone
218declare float @llvm.AMDIL.exp.(float) #3
219
220; Function Attrs: nounwind readonly
221declare float @llvm.pow.f32(float, float) #4
222
223; Function Attrs: nounwind readnone
224declare i32 @llvm.SI.packf16(float, float) #1
225
226; This checks for a bug in the FixSGPRCopies pass where VReg96
227; registers were being identified as an SGPR regclass which was causing
228; an assertion failure.
229
230; CHECK-LABEL: @sample_v3
231; CHECK: IMAGE_SAMPLE
232; CHECK: IMAGE_SAMPLE
233; CHECK: EXP
234; CHECK: S_ENDPGM
235define void @sample_v3([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
236
237entry:
238  %21 = getelementptr [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 0
239  %22 = load <16 x i8> addrspace(2)* %21, !tbaa !2
240  %23 = call float @llvm.SI.load.const(<16 x i8> %22, i32 16)
241  %24 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 0
242  %25 = load <32 x i8> addrspace(2)* %24, !tbaa !2
243  %26 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 0
244  %27 = load <16 x i8> addrspace(2)* %26, !tbaa !2
245  %28 = fcmp oeq float %23, 0.0
246  br i1 %28, label %if, label %else
247
248if:
249  %val.if = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> <i32 0, i32 0>, <32 x i8> %25, <16 x i8> %27, i32 2)
250  %val.if.0 = extractelement <4 x float> %val.if, i32 0
251  %val.if.1 = extractelement <4 x float> %val.if, i32 1
252  %val.if.2 = extractelement <4 x float> %val.if, i32 2
253  br label %endif
254
255else:
256  %val.else = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> <i32 1, i32 0>, <32 x i8> %25, <16 x i8> %27, i32 2)
257  %val.else.0 = extractelement <4 x float> %val.else, i32 0
258  %val.else.1 = extractelement <4 x float> %val.else, i32 1
259  %val.else.2 = extractelement <4 x float> %val.else, i32 2
260  br label %endif
261
262endif:
263  %val.0 = phi float [%val.if.0, %if], [%val.else.0, %else]
264  %val.1 = phi float [%val.if.1, %if], [%val.else.1, %else]
265  %val.2 = phi float [%val.if.2, %if], [%val.else.2, %else]
266  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %val.0, float %val.1, float %val.2, float 0.0)
267  ret void
268}
269
270!2 = metadata !{metadata !"const", null, i32 1}
271
272; CHECK-LABEL: @copy1
273; CHECK: BUFFER_LOAD_DWORD
274; CHECK: V_ADD
275; CHECK: S_ENDPGM
276define void @copy1(float addrspace(1)* %out, float addrspace(1)* %in0) {
277entry:
278  %0 = load float addrspace(1)* %in0
279  %1 = fcmp oeq float %0, 0.0
280  br i1 %1, label %if0, label %endif
281
282if0:
283  %2 = bitcast float %0 to i32
284  %3 = fcmp olt float %0, 0.0
285  br i1 %3, label %if1, label %endif
286
287if1:
288  %4 = add i32 %2, 1
289  br label %endif
290
291endif:
292  %5 = phi i32 [ 0, %entry ], [ %2, %if0 ], [ %4, %if1 ]
293  %6 = bitcast i32 %5 to float
294  store float %6, float addrspace(1)* %out
295  ret void
296}
297
298; This test is just checking that we don't crash / assertion fail.
299; CHECK-LABEL: @copy2
300; CHECK: S_ENDPGM
301
302define void @copy2([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
303entry:
304  br label %LOOP68
305
306LOOP68:
307  %temp4.7 = phi float [ 0.000000e+00, %entry ], [ %v, %ENDIF69 ]
308  %t = phi i32 [ 20, %entry ], [ %x, %ENDIF69 ]
309  %g = icmp eq i32 0, %t
310  %l = bitcast float %temp4.7 to i32
311  br i1 %g, label %IF70, label %ENDIF69
312
313IF70:
314  %q = icmp ne i32 %l, 13
315  %temp.8 = select i1 %q, float 1.000000e+00, float 0.000000e+00
316  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %temp.8, float 0.000000e+00, float 0.000000e+00, float 1.000000e+00)
317  ret void
318
319ENDIF69:
320  %u = add i32 %l, %t
321  %v = bitcast i32 %u to float
322  %x = add i32 %t, -1
323  br label %LOOP68
324}
325
326attributes #0 = { "ShaderType"="0" }
327
328