1;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG %s 2;RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=SI %s 3;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck --check-prefix=VI %s 4 5;EG: {{^}}shl_v2i32: 6;EG: LSHL {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} 7;EG: LSHL {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} 8 9;SI: {{^}}shl_v2i32: 10;SI: v_lshl_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} 11;SI: v_lshl_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} 12 13;VI: {{^}}shl_v2i32: 14;VI: v_lshlrev_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} 15;VI: v_lshlrev_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} 16 17define void @shl_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) { 18 %b_ptr = getelementptr <2 x i32> addrspace(1)* %in, i32 1 19 %a = load <2 x i32> addrspace(1) * %in 20 %b = load <2 x i32> addrspace(1) * %b_ptr 21 %result = shl <2 x i32> %a, %b 22 store <2 x i32> %result, <2 x i32> addrspace(1)* %out 23 ret void 24} 25 26;EG: {{^}}shl_v4i32: 27;EG: LSHL {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} 28;EG: LSHL {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} 29;EG: LSHL {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} 30;EG: LSHL {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} 31 32;SI: {{^}}shl_v4i32: 33;SI: v_lshl_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} 34;SI: v_lshl_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} 35;SI: v_lshl_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} 36;SI: v_lshl_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} 37 38;VI: {{^}}shl_v4i32: 39;VI: v_lshlrev_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} 40;VI: v_lshlrev_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} 41;VI: v_lshlrev_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} 42;VI: v_lshlrev_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} 43 44define void @shl_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) { 45 %b_ptr = getelementptr <4 x i32> addrspace(1)* %in, i32 1 46 %a = load <4 x i32> addrspace(1) * %in 47 %b = load <4 x i32> addrspace(1) * %b_ptr 48 %result = shl <4 x i32> %a, %b 49 store <4 x i32> %result, <4 x i32> addrspace(1)* %out 50 ret void 51} 52 53;EG: {{^}}shl_i64: 54;EG: SUB_INT {{\*? *}}[[COMPSH:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHIFT:T[0-9]+\.[XYZW]]] 55;EG: LSHR {{\* *}}[[TEMP:T[0-9]+\.[XYZW]]], [[OPLO:T[0-9]+\.[XYZW]]], {{[[COMPSH]]|PV.[XYZW]}} 56;EG: LSHR {{\*? *}}[[OVERF:T[0-9]+\.[XYZW]]], {{[[TEMP]]|PV.[XYZW]}}, 1 57;EG_CHECK-DAG: ADD_INT {{\*? *}}[[BIGSH:T[0-9]+\.[XYZW]]], [[SHIFT]], literal 58;EG-DAG: LSHL {{\*? *}}[[HISMTMP:T[0-9]+\.[XYZW]]], [[OPHI:T[0-9]+\.[XYZW]]], [[SHIFT]] 59;EG-DAG: OR_INT {{\*? *}}[[HISM:T[0-9]+\.[XYZW]]], {{[[HISMTMP]]|PV.[XYZW]}}, {{[[OVERF]]|PV.[XYZW]}} 60;EG-DAG: LSHL {{\*? *}}[[LOSM:T[0-9]+\.[XYZW]]], [[OPLO]], {{PS|[[SHIFT]]}} 61;EG-DAG: SETGT_UINT {{\*? *}}[[RESC:T[0-9]+\.[XYZW]]], [[SHIFT]], literal 62;EG-DAG: CNDE_INT {{\*? *}}[[RESLO:T[0-9]+\.[XYZW]]], {{T[0-9]+\.[XYZW]}} 63;EG-DAG: CNDE_INT {{\*? *}}[[RESHI:T[0-9]+\.[XYZW]]], {{T[0-9]+\.[XYZW], .*}}, 0.0 64 65;SI: {{^}}shl_i64: 66;SI: v_lshl_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}} 67 68;VI: {{^}}shl_i64: 69;VI: v_lshlrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}} 70 71define void @shl_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in) { 72 %b_ptr = getelementptr i64 addrspace(1)* %in, i64 1 73 %a = load i64 addrspace(1) * %in 74 %b = load i64 addrspace(1) * %b_ptr 75 %result = shl i64 %a, %b 76 store i64 %result, i64 addrspace(1)* %out 77 ret void 78} 79 80;EG: {{^}}shl_v2i64: 81;EG-DAG: SUB_INT {{\*? *}}[[COMPSHA:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHA:T[0-9]+\.[XYZW]]] 82;EG-DAG: SUB_INT {{\*? *}}[[COMPSHB:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHB:T[0-9]+\.[XYZW]]] 83;EG-DAG: LSHR {{\*? *}}[[COMPSHA]] 84;EG-DAG: LSHR {{\*? *}}[[COMPSHB]] 85;EG-DAG: LSHR {{.*}}, 1 86;EG-DAG: LSHR {{.*}}, 1 87;EG-DAG: ADD_INT {{\*? *}}[[BIGSHA:T[0-9]+\.[XYZW]]]{{.*}}, literal 88;EG-DAG: ADD_INT {{\*? *}}[[BIGSHB:T[0-9]+\.[XYZW]]]{{.*}}, literal 89;EG-DAG: LSHL {{.*}}, [[SHA]] 90;EG-DAG: LSHL {{.*}}, [[SHB]] 91;EG-DAG: LSHL {{.*}}, [[SHA]] 92;EG-DAG: LSHL {{.*}}, [[SHB]] 93;EG-DAG: LSHL 94;EG-DAG: LSHL 95;EG-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHA]], literal 96;EG-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHB]], literal 97;EG-DAG: CNDE_INT {{.*}}, 0.0 98;EG-DAG: CNDE_INT {{.*}}, 0.0 99;EG-DAG: CNDE_INT 100;EG-DAG: CNDE_INT 101 102;SI: {{^}}shl_v2i64: 103;SI: v_lshl_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}} 104;SI: v_lshl_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}} 105 106;VI: {{^}}shl_v2i64: 107;VI: v_lshlrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}} 108;VI: v_lshlrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}} 109 110define void @shl_v2i64(<2 x i64> addrspace(1)* %out, <2 x i64> addrspace(1)* %in) { 111 %b_ptr = getelementptr <2 x i64> addrspace(1)* %in, i64 1 112 %a = load <2 x i64> addrspace(1) * %in 113 %b = load <2 x i64> addrspace(1) * %b_ptr 114 %result = shl <2 x i64> %a, %b 115 store <2 x i64> %result, <2 x i64> addrspace(1)* %out 116 ret void 117} 118 119;EG: {{^}}shl_v4i64: 120;EG-DAG: SUB_INT {{\*? *}}[[COMPSHA:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHA:T[0-9]+\.[XYZW]]] 121;EG-DAG: SUB_INT {{\*? *}}[[COMPSHB:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHB:T[0-9]+\.[XYZW]]] 122;EG-DAG: SUB_INT {{\*? *}}[[COMPSHC:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHC:T[0-9]+\.[XYZW]]] 123;EG-DAG: SUB_INT {{\*? *}}[[COMPSHD:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHD:T[0-9]+\.[XYZW]]] 124;EG-DAG: LSHR {{\*? *}}[[COMPSHA]] 125;EG-DAG: LSHR {{\*? *}}[[COMPSHB]] 126;EG-DAG: LSHR {{\*? *}}[[COMPSHC]] 127;EG-DAG: LSHR {{\*? *}}[[COMPSHD]] 128;EG-DAG: LSHR {{.*}}, 1 129;EG-DAG: LSHR {{.*}}, 1 130;EG-DAG: LSHR {{.*}}, 1 131;EG-DAG: LSHR {{.*}}, 1 132;EG-DAG: ADD_INT {{\*? *}}[[BIGSHA:T[0-9]+\.[XYZW]]]{{.*}}, literal 133;EG-DAG: ADD_INT {{\*? *}}[[BIGSHB:T[0-9]+\.[XYZW]]]{{.*}}, literal 134;EG-DAG: ADD_INT {{\*? *}}[[BIGSHC:T[0-9]+\.[XYZW]]]{{.*}}, literal 135;EG-DAG: ADD_INT {{\*? *}}[[BIGSHD:T[0-9]+\.[XYZW]]]{{.*}}, literal 136;EG-DAG: LSHL {{.*}}, [[SHA]] 137;EG-DAG: LSHL {{.*}}, [[SHB]] 138;EG-DAG: LSHL {{.*}}, [[SHC]] 139;EG-DAG: LSHL {{.*}}, [[SHD]] 140;EG-DAG: LSHL {{.*}}, [[SHA]] 141;EG-DAG: LSHL {{.*}}, [[SHB]] 142;EG-DAG: LSHL {{.*}}, [[SHC]] 143;EG-DAG: LSHL {{.*}}, [[SHD]] 144;EG-DAG: LSHL 145;EG-DAG: LSHL 146;EG-DAG: LSHL 147;EG-DAG: LSHL 148;EG-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHA]], literal 149;EG-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHB]], literal 150;EG-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHC]], literal 151;EG-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHD]], literal 152;EG-DAG: CNDE_INT {{.*}}, 0.0 153;EG-DAG: CNDE_INT {{.*}}, 0.0 154;EG-DAG: CNDE_INT {{.*}}, 0.0 155;EG-DAG: CNDE_INT {{.*}}, 0.0 156;EG-DAG: CNDE_INT 157;EG-DAG: CNDE_INT 158;EG-DAG: CNDE_INT 159;EG-DAG: CNDE_INT 160 161;SI: {{^}}shl_v4i64: 162;SI: v_lshl_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}} 163;SI: v_lshl_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}} 164;SI: v_lshl_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}} 165;SI: v_lshl_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}} 166 167;VI: {{^}}shl_v4i64: 168;VI: v_lshlrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}} 169;VI: v_lshlrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}} 170;VI: v_lshlrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}} 171;VI: v_lshlrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}} 172 173define void @shl_v4i64(<4 x i64> addrspace(1)* %out, <4 x i64> addrspace(1)* %in) { 174 %b_ptr = getelementptr <4 x i64> addrspace(1)* %in, i64 1 175 %a = load <4 x i64> addrspace(1) * %in 176 %b = load <4 x i64> addrspace(1) * %b_ptr 177 %result = shl <4 x i64> %a, %b 178 store <4 x i64> %result, <4 x i64> addrspace(1)* %out 179 ret void 180} 181