1;RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck %s
2
3; This shader has the potential to generated illegal VGPR to SGPR copies if
4; the wrong register class is used for the REG_SEQUENCE instructions.
5
6; CHECK: @main
7; CHECK: IMAGE_SAMPLE_B v{{\[[0-9]:[0-9]\]}}, 15, 0, 0, 0, 0, 0, 0, 0, v{{\[[0-9]:[0-9]\]}}
8
9define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
10main_body:
11  %20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
12  %21 = load <16 x i8> addrspace(2)* %20, !tbaa !1
13  %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 16)
14  %23 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
15  %24 = load <32 x i8> addrspace(2)* %23, !tbaa !1
16  %25 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
17  %26 = load <16 x i8> addrspace(2)* %25, !tbaa !1
18  %27 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
19  %28 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
20  %29 = bitcast float %22 to i32
21  %30 = bitcast float %27 to i32
22  %31 = bitcast float %28 to i32
23  %32 = insertelement <4 x i32> undef, i32 %29, i32 0
24  %33 = insertelement <4 x i32> %32, i32 %30, i32 1
25  %34 = insertelement <4 x i32> %33, i32 %31, i32 2
26  %35 = insertelement <4 x i32> %34, i32 undef, i32 3
27  %36 = call <4 x float> @llvm.SI.sampleb.v4i32(<4 x i32> %35, <32 x i8> %24, <16 x i8> %26, i32 2)
28  %37 = extractelement <4 x float> %36, i32 0
29  %38 = extractelement <4 x float> %36, i32 1
30  %39 = extractelement <4 x float> %36, i32 2
31  %40 = extractelement <4 x float> %36, i32 3
32  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %37, float %38, float %39, float %40)
33  ret void
34}
35
36; Function Attrs: nounwind readnone
37declare float @llvm.SI.load.const(<16 x i8>, i32) #1
38
39; Function Attrs: nounwind readnone
40declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
41
42; Function Attrs: nounwind readnone
43declare <4 x float> @llvm.SI.sampleb.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32) #1
44
45declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
46
47attributes #0 = { "ShaderType"="0" }
48attributes #1 = { nounwind readnone }
49
50!0 = metadata !{metadata !"const", null}
51!1 = metadata !{metadata !0, metadata !0, i64 0, i32 1}
52