1; RUN: llc < %s -march=thumb -mcpu=cortex-a8 | FileCheck %s -check-prefix=ARMv7A
2; RUN: llc < %s -march=thumb -mcpu=cortex-m3 | FileCheck %s -check-prefix=ARMv7M
3
4define i32 @test1(i32 %x) {
5; ARMv7A: test1
6; ARMv7A: uxtb16 r0, r0
7
8; ARMv7M: test1
9; ARMv7M: bic r0, r0, #-16711936
10	%tmp1 = and i32 %x, 16711935		; <i32> [#uses=1]
11	ret i32 %tmp1
12}
13
14; PR7503
15define i32 @test2(i32 %x) {
16; ARMv7A: test2
17; ARMv7A: uxtb16  r0, r0, ror #8
18
19; ARMv7M: test2
20; ARMv7M: mov.w r1, #16711935
21; ARMv7M: and.w r0, r1, r0, lsr #8
22	%tmp1 = lshr i32 %x, 8		; <i32> [#uses=1]
23	%tmp2 = and i32 %tmp1, 16711935		; <i32> [#uses=1]
24	ret i32 %tmp2
25}
26
27define i32 @test3(i32 %x) {
28; ARMv7A: test3
29; ARMv7A: uxtb16  r0, r0, ror #8
30
31; ARMv7M: test3
32; ARMv7M: mov.w r1, #16711935
33; ARMv7M: and.w r0, r1, r0, lsr #8
34	%tmp1 = lshr i32 %x, 8		; <i32> [#uses=1]
35	%tmp2 = and i32 %tmp1, 16711935		; <i32> [#uses=1]
36	ret i32 %tmp2
37}
38
39define i32 @test4(i32 %x) {
40; ARMv7A: test4
41; ARMv7A: uxtb16  r0, r0, ror #8
42
43; ARMv7M: test4
44; ARMv7M: mov.w r1, #16711935
45; ARMv7M: and.w r0, r1, r0, lsr #8
46	%tmp1 = lshr i32 %x, 8		; <i32> [#uses=1]
47	%tmp6 = and i32 %tmp1, 16711935		; <i32> [#uses=1]
48	ret i32 %tmp6
49}
50
51define i32 @test5(i32 %x) {
52; ARMv7A: test5
53; ARMv7A: uxtb16  r0, r0, ror #8
54
55; ARMv7M: test5
56; ARMv7M: mov.w r1, #16711935
57; ARMv7M: and.w r0, r1, r0, lsr #8
58	%tmp1 = lshr i32 %x, 8		; <i32> [#uses=1]
59	%tmp2 = and i32 %tmp1, 16711935		; <i32> [#uses=1]
60	ret i32 %tmp2
61}
62
63define i32 @test6(i32 %x) {
64; ARMv7A: test6
65; ARMv7A: uxtb16  r0, r0, ror #16
66
67; ARMv7M: test6
68; ARMv7M: mov.w r1, #16711935
69; ARMv7M: and.w r0, r1, r0, ror #16
70	%tmp1 = lshr i32 %x, 16		; <i32> [#uses=1]
71	%tmp2 = and i32 %tmp1, 255		; <i32> [#uses=1]
72	%tmp4 = shl i32 %x, 16		; <i32> [#uses=1]
73	%tmp5 = and i32 %tmp4, 16711680		; <i32> [#uses=1]
74	%tmp6 = or i32 %tmp2, %tmp5		; <i32> [#uses=1]
75	ret i32 %tmp6
76}
77
78define i32 @test7(i32 %x) {
79; ARMv7A: test7
80; ARMv7A: uxtb16  r0, r0, ror #16
81
82; ARMv7M: test7
83; ARMv7M: mov.w r1, #16711935
84; ARMv7M: and.w r0, r1, r0, ror #16
85	%tmp1 = lshr i32 %x, 16		; <i32> [#uses=1]
86	%tmp2 = and i32 %tmp1, 255		; <i32> [#uses=1]
87	%tmp4 = shl i32 %x, 16		; <i32> [#uses=1]
88	%tmp5 = and i32 %tmp4, 16711680		; <i32> [#uses=1]
89	%tmp6 = or i32 %tmp2, %tmp5		; <i32> [#uses=1]
90	ret i32 %tmp6
91}
92
93define i32 @test8(i32 %x) {
94; ARMv7A: test8
95; ARMv7A: uxtb16  r0, r0, ror #24
96
97; ARMv7M: test8
98; ARMv7M: mov.w r1, #16711935
99; ARMv7M: and.w r0, r1, r0, ror #24
100	%tmp1 = shl i32 %x, 8		; <i32> [#uses=1]
101	%tmp2 = and i32 %tmp1, 16711680		; <i32> [#uses=1]
102	%tmp5 = lshr i32 %x, 24		; <i32> [#uses=1]
103	%tmp6 = or i32 %tmp2, %tmp5		; <i32> [#uses=1]
104	ret i32 %tmp6
105}
106
107define i32 @test9(i32 %x) {
108; ARMv7A: test9
109; ARMv7A: uxtb16  r0, r0, ror #24
110
111; ARMv7M: test9
112; ARMv7M: mov.w r1, #16711935
113; ARMv7M: and.w r0, r1, r0, ror #24
114	%tmp1 = lshr i32 %x, 24		; <i32> [#uses=1]
115	%tmp4 = shl i32 %x, 8		; <i32> [#uses=1]
116	%tmp5 = and i32 %tmp4, 16711680		; <i32> [#uses=1]
117	%tmp6 = or i32 %tmp5, %tmp1		; <i32> [#uses=1]
118	ret i32 %tmp6
119}
120
121define i32 @test10(i32 %p0) {
122; ARMv7A: test10
123; ARMv7A: mov.w r1, #16253176
124; ARMv7A: and.w r0, r1, r0, lsr #7
125; ARMv7A: lsrs  r1, r0, #5
126; ARMv7A: uxtb16  r1, r1
127; ARMv7A: orrs r0, r1
128
129; ARMv7M: test10
130; ARMv7M: mov.w r1, #16253176
131; ARMv7M: and.w r0, r1, r0, lsr #7
132; ARMv7M: mov.w r1, #458759
133; ARMv7M: and.w r1, r1, r0, lsr #5
134; ARMv7M: orrs r0, r1
135	%tmp1 = lshr i32 %p0, 7		; <i32> [#uses=1]
136	%tmp2 = and i32 %tmp1, 16253176		; <i32> [#uses=2]
137	%tmp4 = lshr i32 %tmp2, 5		; <i32> [#uses=1]
138	%tmp5 = and i32 %tmp4, 458759		; <i32> [#uses=1]
139	%tmp7 = or i32 %tmp5, %tmp2		; <i32> [#uses=1]
140	ret i32 %tmp7
141}
142