1; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -mattr=+avx | FileCheck %s
2
3; Check that we perform a scalar XOR on i32.
4
5; CHECK: pull_bitcast
6; CHECK: xorl
7; CHECK: ret
8define void @pull_bitcast (<4 x i8>* %pA, <4 x i8>* %pB) {
9  %A = load <4 x i8>* %pA
10  %B = load <4 x i8>* %pB
11  %C = xor <4 x i8> %A, %B
12  store <4 x i8> %C, <4 x i8>* %pA
13  ret void
14}
15
16; CHECK: multi_use_swizzle
17; CHECK: mov
18; CHECK-NEXT: shuf
19; CHECK-NEXT: shuf
20; CHECK-NEXT: shuf
21; CHECK-NEXT: xor
22; CHECK-NEXT: ret
23define <4 x i32> @multi_use_swizzle (<4 x i32>* %pA, <4 x i32>* %pB) {
24  %A = load <4 x i32>* %pA
25  %B = load <4 x i32>* %pB
26  %S = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 1, i32 1, i32 5, i32 6>
27  %S1 = shufflevector <4 x i32> %S, <4 x i32> undef, <4 x i32> <i32 1, i32 3, i32 2, i32 2>
28  %S2 = shufflevector <4 x i32> %S, <4 x i32> undef, <4 x i32> <i32 2, i32 1, i32 0, i32 2>
29  %R = xor <4 x i32> %S1, %S2
30  ret <4 x i32> %R
31}
32
33; CHECK: pull_bitcast2
34; CHECK: xorl
35; CHECK: ret
36define <4 x i8> @pull_bitcast2 (<4 x i8>* %pA, <4 x i8>* %pB, <4 x i8>* %pC) {
37  %A = load <4 x i8>* %pA
38  store <4 x i8> %A, <4 x i8>* %pC
39  %B = load <4 x i8>* %pB
40  %C = xor <4 x i8> %A, %B
41  store <4 x i8> %C, <4 x i8>* %pA
42  ret <4 x i8> %C
43}
44
45
46
47; CHECK: reverse_1
48; CHECK-NOT: shuf
49; CHECK: ret
50define <4 x i32> @reverse_1 (<4 x i32>* %pA, <4 x i32>* %pB) {
51  %A = load <4 x i32>* %pA
52  %B = load <4 x i32>* %pB
53  %S = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
54  %S1 = shufflevector <4 x i32> %S, <4 x i32> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
55  ret <4 x i32> %S1
56}
57
58
59; CHECK: no_reverse_shuff
60; CHECK: shuf
61; CHECK: ret
62define <4 x i32> @no_reverse_shuff (<4 x i32>* %pA, <4 x i32>* %pB) {
63  %A = load <4 x i32>* %pA
64  %B = load <4 x i32>* %pB
65  %S = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
66  %S1 = shufflevector <4 x i32> %S, <4 x i32> undef, <4 x i32> <i32 3, i32 2, i32 3, i32 2>
67  ret <4 x i32> %S1
68}
69