1; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -mattr=+avx | FileCheck %s
2
3;;; Shift left
4; CHECK: vpslld
5; CHECK: vpslld
6define <8 x i32> @vshift00(<8 x i32> %a) nounwind readnone {
7  %s = shl <8 x i32> %a, <i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32
82>
9  ret <8 x i32> %s
10}
11
12; CHECK: vpsllw
13; CHECK: vpsllw
14define <16 x i16> @vshift01(<16 x i16> %a) nounwind readnone {
15  %s = shl <16 x i16> %a, <i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2>
16  ret <16 x i16> %s
17}
18
19; CHECK: vpsllq
20; CHECK: vpsllq
21define <4 x i64> @vshift02(<4 x i64> %a) nounwind readnone {
22  %s = shl <4 x i64> %a, <i64 2, i64 2, i64 2, i64 2>
23  ret <4 x i64> %s
24}
25
26;;; Logical Shift right
27; CHECK: vpsrld
28; CHECK: vpsrld
29define <8 x i32> @vshift03(<8 x i32> %a) nounwind readnone {
30  %s = lshr <8 x i32> %a, <i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32
312>
32  ret <8 x i32> %s
33}
34
35; CHECK: vpsrlw
36; CHECK: vpsrlw
37define <16 x i16> @vshift04(<16 x i16> %a) nounwind readnone {
38  %s = lshr <16 x i16> %a, <i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2>
39  ret <16 x i16> %s
40}
41
42; CHECK: vpsrlq
43; CHECK: vpsrlq
44define <4 x i64> @vshift05(<4 x i64> %a) nounwind readnone {
45  %s = lshr <4 x i64> %a, <i64 2, i64 2, i64 2, i64 2>
46  ret <4 x i64> %s
47}
48
49;;; Arithmetic Shift right
50; CHECK: vpsrad
51; CHECK: vpsrad
52define <8 x i32> @vshift06(<8 x i32> %a) nounwind readnone {
53  %s = ashr <8 x i32> %a, <i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32
542>
55  ret <8 x i32> %s
56}
57
58; CHECK: vpsraw
59; CHECK: vpsraw
60define <16 x i16> @vshift07(<16 x i16> %a) nounwind readnone {
61  %s = ashr <16 x i16> %a, <i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2>
62  ret <16 x i16> %s
63}
64
65; CHECK: vpsrlw
66; CHECK: pand
67; CHECK: pxor
68; CHECK: psubb
69; CHECK: vpsrlw
70; CHECK: pand
71; CHECK: pxor
72; CHECK: psubb
73define <32 x i8> @vshift09(<32 x i8> %a) nounwind readnone {
74  %s = ashr <32 x i8> %a, <i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2>
75  ret <32 x i8> %s
76}
77
78; CHECK: pxor
79; CHECK: pcmpgtb
80; CHECK: pcmpgtb
81define <32 x i8> @vshift10(<32 x i8> %a) nounwind readnone {
82  %s = ashr <32 x i8> %a, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>
83  ret <32 x i8> %s
84}
85
86; CHECK: vpsrlw
87; CHECK: pand
88; CHECK: vpsrlw
89; CHECK: pand
90define <32 x i8> @vshift11(<32 x i8> %a) nounwind readnone {
91  %s = lshr <32 x i8> %a, <i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2>
92  ret <32 x i8> %s
93}
94
95; CHECK: vpsllw
96; CHECK: pand
97; CHECK: vpsllw
98; CHECK: pand
99define <32 x i8> @vshift12(<32 x i8> %a) nounwind readnone {
100  %s = shl <32 x i8> %a, <i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2>
101  ret <32 x i8> %s
102}
103
104;;; Support variable shifts
105; CHECK: _vshift08
106; CHECK: vpslld $23
107; CHECK: vextractf128 $1
108; CHECK: vpslld $23
109; CHECK: ret
110define <8 x i32> @vshift08(<8 x i32> %a) nounwind {
111  %bitop = shl <8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>, %a
112  ret <8 x i32> %bitop
113}
114
115; PR15141
116; CHECK: _vshift13:
117; CHECK-NOT: vpsll
118; CHECK-NOT: vcvttps2dq
119; CHECK: vpmulld
120define <4 x i32> @vshift13(<4 x i32> %in) {
121  %T = shl <4 x i32> %in, <i32 0, i32 1, i32 2, i32 4>
122  ret <4 x i32> %T
123}
124
125;;; Uses shifts for sign extension
126; CHECK: _sext_v16i16
127; CHECK: vpsllw
128; CHECK: vpsraw
129; CHECK: vpsllw
130; CHECK: vpsraw
131; CHECK: vinsertf128
132define <16 x i16> @sext_v16i16(<16 x i16> %a) nounwind {
133  %b = trunc <16 x i16> %a to <16 x i8>
134  %c = sext <16 x i8> %b to <16 x i16>
135  ret <16 x i16> %c
136}
137
138; CHECK: _sext_v8i32
139; CHECK: vpslld
140; CHECK: vpsrad
141; CHECK: vpslld
142; CHECK: vpsrad
143; CHECK: vinsertf128
144define <8 x i32> @sext_v8i32(<8 x i32> %a) nounwind {
145  %b = trunc <8 x i32> %a to <8 x i16>
146  %c = sext <8 x i16> %b to <8 x i32>
147  ret <8 x i32> %c
148}
149