1; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=core-avx2 -mattr=+avx2 | FileCheck %s 2 3; CHECK: trunc4 4; CHECK: vpermd 5; CHECK-NOT: vinsert 6; CHECK: ret 7define <4 x i32> @trunc4(<4 x i64> %A) nounwind { 8 %B = trunc <4 x i64> %A to <4 x i32> 9 ret <4 x i32>%B 10} 11 12; CHECK: trunc8 13; CHECK: vpshufb 14; CHECK-NOT: vinsert 15; CHECK: ret 16 17define <8 x i16> @trunc8(<8 x i32> %A) nounwind { 18 %B = trunc <8 x i32> %A to <8 x i16> 19 ret <8 x i16>%B 20} 21 22; CHECK: sext4 23; CHECK: vpmovsxdq 24; CHECK-NOT: vinsert 25; CHECK: ret 26define <4 x i64> @sext4(<4 x i32> %A) nounwind { 27 %B = sext <4 x i32> %A to <4 x i64> 28 ret <4 x i64>%B 29} 30 31; CHECK: sext8 32; CHECK: vpmovsxwd 33; CHECK-NOT: vinsert 34; CHECK: ret 35define <8 x i32> @sext8(<8 x i16> %A) nounwind { 36 %B = sext <8 x i16> %A to <8 x i32> 37 ret <8 x i32>%B 38} 39 40; CHECK: zext4 41; CHECK: vpmovzxdq 42; CHECK-NOT: vinsert 43; CHECK: ret 44define <4 x i64> @zext4(<4 x i32> %A) nounwind { 45 %B = zext <4 x i32> %A to <4 x i64> 46 ret <4 x i64>%B 47} 48 49; CHECK: zext8 50; CHECK: vpmovzxwd 51; CHECK-NOT: vinsert 52; CHECK: ret 53define <8 x i32> @zext8(<8 x i16> %A) nounwind { 54 %B = zext <8 x i16> %A to <8 x i32> 55 ret <8 x i32>%B 56} 57; CHECK: zext_8i8_8i32 58; CHECK: vpmovzxwd 59; CHECK: vpand 60; CHECK: ret 61define <8 x i32> @zext_8i8_8i32(<8 x i8> %A) nounwind { 62 %B = zext <8 x i8> %A to <8 x i32> 63 ret <8 x i32>%B 64} 65 66; CHECK-LABEL: zext_16i8_16i16: 67; CHECK: vpmovzxbw 68; CHECK-NOT: vinsert 69; CHECK: ret 70define <16 x i16> @zext_16i8_16i16(<16 x i8> %z) { 71 %t = zext <16 x i8> %z to <16 x i16> 72 ret <16 x i16> %t 73} 74 75; CHECK-LABEL: sext_16i8_16i16: 76; CHECK: vpmovsxbw 77; CHECK-NOT: vinsert 78; CHECK: ret 79define <16 x i16> @sext_16i8_16i16(<16 x i8> %z) { 80 %t = sext <16 x i8> %z to <16 x i16> 81 ret <16 x i16> %t 82} 83 84; CHECK-LABEL: trunc_16i16_16i8: 85; CHECK: vpshufb 86; CHECK: vpshufb 87; CHECK: vpor 88; CHECK: ret 89define <16 x i8> @trunc_16i16_16i8(<16 x i16> %z) { 90 %t = trunc <16 x i16> %z to <16 x i8> 91 ret <16 x i8> %t 92} 93 94; CHECK: load_sext_test1 95; CHECK: vpmovsxdq (%r{{[^,]*}}), %ymm{{.*}} 96; CHECK: ret 97define <4 x i64> @load_sext_test1(<4 x i32> *%ptr) { 98 %X = load <4 x i32>* %ptr 99 %Y = sext <4 x i32> %X to <4 x i64> 100 ret <4 x i64>%Y 101} 102 103; CHECK: load_sext_test2 104; CHECK: vpmovsxbq (%r{{[^,]*}}), %ymm{{.*}} 105; CHECK: ret 106define <4 x i64> @load_sext_test2(<4 x i8> *%ptr) { 107 %X = load <4 x i8>* %ptr 108 %Y = sext <4 x i8> %X to <4 x i64> 109 ret <4 x i64>%Y 110} 111 112; CHECK: load_sext_test3 113; CHECK: vpmovsxwq (%r{{[^,]*}}), %ymm{{.*}} 114; CHECK: ret 115define <4 x i64> @load_sext_test3(<4 x i16> *%ptr) { 116 %X = load <4 x i16>* %ptr 117 %Y = sext <4 x i16> %X to <4 x i64> 118 ret <4 x i64>%Y 119} 120 121; CHECK: load_sext_test4 122; CHECK: vpmovsxwd (%r{{[^,]*}}), %ymm{{.*}} 123; CHECK: ret 124define <8 x i32> @load_sext_test4(<8 x i16> *%ptr) { 125 %X = load <8 x i16>* %ptr 126 %Y = sext <8 x i16> %X to <8 x i32> 127 ret <8 x i32>%Y 128} 129 130; CHECK: load_sext_test5 131; CHECK: vpmovsxbd (%r{{[^,]*}}), %ymm{{.*}} 132; CHECK: ret 133define <8 x i32> @load_sext_test5(<8 x i8> *%ptr) { 134 %X = load <8 x i8>* %ptr 135 %Y = sext <8 x i8> %X to <8 x i32> 136 ret <8 x i32>%Y 137} 138