1; RUN: llc < %s -march=x86 -mattr=+sse2 -mcpu=yonah | FileCheck %s
2; RUN: llc < %s -march=x86-64 -mattr=+sse2 -mcpu=core2 | FileCheck %s
3; RUN: llc < %s -march=x86-64 -mattr=+avx -mcpu=btver2 | FileCheck %s
4
5target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
6
7define i32 @t(<2 x i64>* %val) nounwind  {
8; CHECK-LABEL: t:
9; CHECK-NOT: movd
10; CHECK: movl 8(
11; CHECK-NEXT: ret
12	%tmp2 = load <2 x i64>* %val, align 16		; <<2 x i64>> [#uses=1]
13	%tmp3 = bitcast <2 x i64> %tmp2 to <4 x i32>		; <<4 x i32>> [#uses=1]
14	%tmp4 = extractelement <4 x i32> %tmp3, i32 2		; <i32> [#uses=1]
15	ret i32 %tmp4
16}
17
18; Case where extractelement of load ends up as undef.
19; (Making sure this doesn't crash.)
20define i32 @t2(<8 x i32>* %xp) {
21; CHECK-LABEL: t2:
22; CHECK: ret
23  %x = load <8 x i32>* %xp
24  %Shuff68 = shufflevector <8 x i32> %x, <8 x i32> undef, <8 x i32> <i32
25undef, i32 7, i32 9, i32 undef, i32 13, i32 15, i32 1, i32 3>
26  %y = extractelement <8 x i32> %Shuff68, i32 0
27  ret i32 %y
28}
29
30; This case could easily end up inf-looping in the DAG combiner due to an
31; low alignment load of the vector which prevents us from reliably forming a
32; narrow load.
33
34; The expected codegen is identical for the AVX case except
35; load/store instructions will have a leading 'v', so we don't
36; need to special-case the checks.
37
38define void @t3() {
39; CHECK-LABEL: t3:
40; CHECK: movupd
41; CHECK: movhpd
42
43bb:
44  %tmp13 = load <2 x double>* undef, align 1
45  %.sroa.3.24.vec.extract = extractelement <2 x double> %tmp13, i32 1
46  store double %.sroa.3.24.vec.extract, double* undef, align 8
47  unreachable
48}
49
50; Case where a load is unary shuffled, then bitcast (to a type with the same
51; number of elements) before extractelement.
52; This is testing for an assertion - the extraction was assuming that the undef
53; second shuffle operand was a post-bitcast type instead of a pre-bitcast type.
54define i64 @t4(<2 x double>* %a) {
55; CHECK-LABEL: t4:
56; CHECK: mov
57; CHECK: ret
58  %b = load <2 x double>* %a, align 16
59  %c = shufflevector <2 x double> %b, <2 x double> %b, <2 x i32> <i32 1, i32 0>
60  %d = bitcast <2 x double> %c to <2 x i64>
61  %e = extractelement <2 x i64> %d, i32 1
62  ret i64 %e
63}
64
65