1; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=corei7-avx| FileCheck %s
2
3; Verify that we generate a single OR instruction for a scalar, vec128, and vec256
4; FNABS(x) operation -> FNEG (FABS(x)).
5; If the FABS() result isn't used, the AND instruction should be eliminated.
6; PR20578: http://llvm.org/bugs/show_bug.cgi?id=20578
7
8define float @scalar_no_abs(float %a) {
9; CHECK-LABEL: scalar_no_abs:
10; CHECK: vorps
11; CHECK-NEXT: retq
12  %fabs = tail call float @fabsf(float %a) #1
13  %fsub = fsub float -0.0, %fabs
14  ret float %fsub
15}
16
17define float @scalar_uses_abs(float %a) {
18; CHECK-LABEL: scalar_uses_abs:
19; CHECK-DAG: vandps
20; CHECK-DAG: vorps
21; CHECK: vmulss
22; CHECK-NEXT: retq
23  %fabs = tail call float @fabsf(float %a) #1
24  %fsub = fsub float -0.0, %fabs
25  %fmul = fmul float %fsub, %fabs
26  ret float %fmul
27}
28
29define <4 x float> @vector128_no_abs(<4 x float> %a) {
30; CHECK-LABEL: vector128_no_abs:
31; CHECK: vorps
32; CHECK-NEXT: retq
33  %fabs = tail call <4 x float> @llvm.fabs.v4f32(< 4 x float> %a) #1
34  %fsub = fsub <4 x float> <float -0.0, float -0.0, float -0.0, float -0.0>, %fabs
35  ret <4 x float> %fsub
36}
37
38define <4 x float> @vector128_uses_abs(<4 x float> %a) {
39; CHECK-LABEL: vector128_uses_abs:
40; CHECK-DAG: vandps
41; CHECK-DAG: vorps
42; CHECK: vmulps
43; CHECK-NEXT: retq
44  %fabs = tail call <4 x float> @llvm.fabs.v4f32(<4 x float> %a) #1
45  %fsub = fsub <4 x float> <float -0.0, float -0.0, float -0.0, float -0.0>, %fabs
46  %fmul = fmul <4 x float> %fsub, %fabs
47  ret <4 x float> %fmul
48}
49
50define <8 x float> @vector256_no_abs(<8 x float> %a) {
51; CHECK-LABEL: vector256_no_abs:
52; CHECK: vorps
53; CHECK-NEXT: retq
54  %fabs = tail call <8 x float> @llvm.fabs.v8f32(< 8 x float> %a) #1
55  %fsub = fsub <8 x float> <float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0>, %fabs
56  ret <8 x float> %fsub
57}
58
59define <8 x float> @vector256_uses_abs(<8 x float> %a) {
60; CHECK-LABEL: vector256_uses_abs:
61; CHECK-DAG: vandps
62; CHECK-DAG: vorps
63; CHECK: vmulps
64; CHECK-NEXT: retq
65  %fabs = tail call <8 x float> @llvm.fabs.v8f32(<8 x float> %a) #1
66  %fsub = fsub <8 x float> <float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0>, %fabs
67  %fmul = fmul <8 x float> %fsub, %fabs
68  ret <8 x float> %fmul
69}
70
71declare <4 x float> @llvm.fabs.v4f32(<4 x float> %p)
72declare <8 x float> @llvm.fabs.v8f32(<8 x float> %p)
73
74declare float @fabsf(float)
75
76attributes #1 = { readnone }
77
78