1; RUN: llc < %s -march=x86
2
3define i32 @test1() nounwind {
4	; Dest is AX, dest type = i32.
5        %tmp4 = call i32 asm sideeffect "FROB $0", "={ax}"()
6        ret i32 %tmp4
7}
8
9define void @test2(i32 %V) nounwind {
10	; input is AX, in type = i32.
11        call void asm sideeffect "FROB $0", "{ax}"(i32 %V)
12        ret void
13}
14
15define void @test3() nounwind {
16        ; FP constant as a memory operand.
17        tail call void asm sideeffect "frob $0", "m"( float 0x41E0000000000000)
18        ret void
19}
20
21define void @test4() nounwind {
22       ; J means a constant in range 0 to 63.
23       tail call void asm sideeffect "bork $0", "J"(i32 37) nounwind
24       ret void
25}
26
27; rdar://9738585
28define i32 @test5() nounwind {
29entry:
30  %0 = tail call i32 asm "test", "=l,~{dirflag},~{fpsr},~{flags}"() nounwind
31  ret i32 0
32}
33
34; rdar://9777108 PR10352
35define void @test6(i1 zeroext %desired) nounwind {
36entry:
37  tail call void asm sideeffect "foo $0", "q,~{dirflag},~{fpsr},~{flags}"(i1 %desired) nounwind
38  ret void
39}
40
41define void @test7(i1 zeroext %desired, i32* %p) nounwind {
42entry:
43  %0 = tail call i8 asm sideeffect "xchg $0, $1", "=r,*m,0,~{memory},~{dirflag},~{fpsr},~{flags}"(i32* %p, i1 %desired) nounwind
44  ret void
45}
46
47; <rdar://problem/11542429>
48; The constrained GR32_ABCD register class of the 'q' constraint requires
49; special handling after the preceding outputs used up eax-edx.
50define void @constrain_abcd(i8* %h) nounwind ssp {
51entry:
52  %0 = call { i32, i32, i32, i32, i32 } asm sideeffect "", "=&r,=&r,=&r,=&r,=&q,r,~{ecx},~{memory},~{dirflag},~{fpsr},~{flags}"(i8* %h) nounwind
53  ret void
54}
55
56; Mix normal and EC defs of the same register.
57define i32 @pr14376() nounwind noinline {
58entry:
59  %asm = tail call i32 asm sideeffect "", "={ax},i,~{eax},~{flags},~{rax}"(i64 61) nounwind
60  ret i32 %asm
61}
62