1; RUN: llc < %s -march=x86 -mcpu=core2 | FileCheck %s 2 3define i32 @t1() nounwind { 4entry: 5 %0 = tail call i32 asm sideeffect inteldialect "mov eax, $1\0A\09mov $0, eax", "=r,r,~{eax},~{dirflag},~{fpsr},~{flags}"(i32 1) nounwind 6 ret i32 %0 7; CHECK: t1 8; CHECK: movl %esp, %ebp 9; CHECK: {{## InlineAsm Start|#APP}} 10; CHECK: .intel_syntax 11; CHECK: mov eax, ecx 12; CHECK: mov ecx, eax 13; CHECK: .att_syntax 14; CHECK: {{## InlineAsm End|#NO_APP}} 15} 16 17define void @t2() nounwind { 18entry: 19 call void asm sideeffect inteldialect "mov eax, $$1", "~{eax},~{dirflag},~{fpsr},~{flags}"() nounwind 20 ret void 21; CHECK: t2 22; CHECK: movl %esp, %ebp 23; CHECK: {{## InlineAsm Start|#APP}} 24; CHECK: .intel_syntax 25; CHECK: mov eax, 1 26; CHECK: .att_syntax 27; CHECK: {{## InlineAsm End|#NO_APP}} 28} 29 30define void @t3(i32 %V) nounwind { 31entry: 32 %V.addr = alloca i32, align 4 33 store i32 %V, i32* %V.addr, align 4 34 call void asm sideeffect inteldialect "mov eax, DWORD PTR [$0]", "*m,~{eax},~{dirflag},~{fpsr},~{flags}"(i32* %V.addr) nounwind 35 ret void 36; CHECK: t3 37; CHECK: movl %esp, %ebp 38; CHECK: {{## InlineAsm Start|#APP}} 39; CHECK: .intel_syntax 40; CHECK: mov eax, DWORD PTR {{[[esp]}} 41; CHECK: .att_syntax 42; CHECK: {{## InlineAsm End|#NO_APP}} 43} 44 45%struct.t18_type = type { i32, i32 } 46 47define i32 @t18() nounwind { 48entry: 49 %foo = alloca %struct.t18_type, align 4 50 %a = getelementptr inbounds %struct.t18_type* %foo, i32 0, i32 0 51 store i32 1, i32* %a, align 4 52 %b = getelementptr inbounds %struct.t18_type* %foo, i32 0, i32 1 53 store i32 2, i32* %b, align 4 54 call void asm sideeffect inteldialect "lea ebx, foo\0A\09mov eax, [ebx].0\0A\09mov [ebx].4, ecx", "~{eax},~{dirflag},~{fpsr},~{flags}"() nounwind 55 %b1 = getelementptr inbounds %struct.t18_type* %foo, i32 0, i32 1 56 %0 = load i32* %b1, align 4 57 ret i32 %0 58; CHECK: t18 59; CHECK: movl %esp, %ebp 60; CHECK: {{## InlineAsm Start|#APP}} 61; CHECK: .intel_syntax 62; CHECK: lea ebx, foo 63; CHECK: mov eax, [ebx].0 64; CHECK: mov [ebx].4, ecx 65; CHECK: .att_syntax 66; CHECK: {{## InlineAsm End|#NO_APP}} 67} 68 69define void @t19_helper() nounwind { 70entry: 71 ret void 72} 73 74define void @t19() nounwind { 75entry: 76 call void asm sideeffect inteldialect "call $0", "r,~{dirflag},~{fpsr},~{flags}"(void ()* @t19_helper) nounwind 77 ret void 78; CHECK-LABEL: t19: 79; CHECK: movl %esp, %ebp 80; CHECK: movl ${{_?}}t19_helper, %eax 81; CHECK: {{## InlineAsm Start|#APP}} 82; CHECK: .intel_syntax 83; CHECK: call eax 84; CHECK: .att_syntax 85; CHECK: {{## InlineAsm End|#NO_APP}} 86} 87 88@results = global [2 x i32] [i32 3, i32 2], align 4 89 90define i32* @t30() nounwind ssp { 91entry: 92 %res = alloca i32*, align 4 93 call void asm sideeffect inteldialect "lea edi, dword ptr $0", "*m,~{edi},~{dirflag},~{fpsr},~{flags}"([2 x i32]* @results) nounwind 94 call void asm sideeffect inteldialect "mov dword ptr $0, edi", "=*m,~{dirflag},~{fpsr},~{flags}"(i32** %res) nounwind 95 %0 = load i32** %res, align 4 96 ret i32* %0 97; CHECK-LABEL: t30: 98; CHECK: movl %esp, %ebp 99; CHECK: {{## InlineAsm Start|#APP}} 100; CHECK: .intel_syntax 101; CHECK: lea edi, dword ptr [{{_?}}results] 102; CHECK: .att_syntax 103; CHECK: {{## InlineAsm End|#NO_APP}} 104; CHECK: {{## InlineAsm Start|#APP}} 105; CHECK: .intel_syntax 106; CHECK: mov dword ptr [esi], edi 107; CHECK: .att_syntax 108; CHECK: {{## InlineAsm End|#NO_APP}} 109; CHECK: movl (%esi), %eax 110} 111