1; RUN: opt < %s -O3 | \
2; RUN:	llc -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -mattr=+avx | FileCheck %s
3
4define <4 x i32> @test1(<4 x float> %a, <4 x float> %b, <4 x i32> %c) {
5  %f = fcmp ult <4 x float> %a, %b
6  %r = select <4 x i1> %f, <4 x i32> %c, <4 x i32> zeroinitializer
7  ret <4 x i32> %r
8; CHECK: test1
9; CHECK: cmpnle
10; CHECK-NEXT: andps
11; CHECK: ret
12}
13
14define <4 x i32> @test2(<4 x float> %a, <4 x float> %b, <4 x i32> %c) {
15  %f = fcmp ult <4 x float> %a, %b
16  %r = select <4 x i1> %f, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, <4 x i32> %c
17  ret <4 x i32> %r
18; CHECK: test2
19; CHECK: cmpnle
20; CHECK-NEXT: orps
21; CHECK: ret
22}
23
24define <4 x i32> @test3(<4 x float> %a, <4 x float> %b, <4 x i32> %c) {
25  %f = fcmp ult <4 x float> %a, %b
26  %r = select <4 x i1> %f, <4 x i32> zeroinitializer, <4 x i32> %c
27  ret <4 x i32> %r
28; CHECK: test3
29; CHECK: cmple
30; CHECK-NEXT: andps
31; CHECK: ret
32}
33
34define <4 x i32> @test4(<4 x float> %a, <4 x float> %b, <4 x i32> %c) {
35  %f = fcmp ult <4 x float> %a, %b
36  %r = select <4 x i1> %f, <4 x i32> %c, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>
37  ret <4 x i32> %r
38; CHECK: test4
39; CHECK: cmple
40; CHECK-NEXT: orps
41; CHECK: ret
42}
43
44define <4 x i32> @test5(<4 x float> %a, <4 x float> %b, <4 x i32> %c) {
45  %f = fcmp ult <4 x float> %a, %b
46  %r = select <4 x i1> %f, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, <4 x i32> zeroinitializer
47  ret <4 x i32> %r
48; CHECK: test5
49; CHECK: cmpnle
50; CHECK-NEXT: ret
51}
52
53define <4 x i32> @test6(<4 x float> %a, <4 x float> %b, <4 x i32> %c) {
54  %f = fcmp ult <4 x float> %a, %b
55  %r = select <4 x i1> %f, <4 x i32> zeroinitializer, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>
56  ret <4 x i32> %r
57; CHECK: test6
58; CHECK: cmple
59; CHECK-NEXT: ret
60}
61
62define <4 x i32> @test7(<4 x float> %a, <4 x float> %b, <4 x i32>* %p) {
63  %f = fcmp ult <4 x float> %a, %b
64  %s = sext <4 x i1> %f to <4 x i32>
65  %l = load <4 x i32>* %p
66  %r = and <4 x i32> %l, %s
67  ret <4 x i32> %r
68; CHECK: test7
69; CHECK: cmpnle
70; CHECK-NEXT: andps
71; CHECK: ret
72}
73