1; RUN: llc < %s -mcpu=nehalem | FileCheck %s
2target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
3target triple = "x86_64-apple-macosx10.7"
4
5; CHECK: f
6;
7; This function contains load / store / and operations that all can execute in
8; any domain.  The only domain-specific operation is the %add = shl... operation
9; which is <4 x i32>.
10;
11; The paddd instruction can only influence the other operations through the loop
12; back-edge. Check that everything is still moved into the integer domain.
13
14define void @f(<4 x i32>* nocapture %p, i32 %n) nounwind uwtable ssp {
15entry:
16  br label %while.body
17
18; Materialize a zeroinitializer and a constant-pool load in the integer domain.
19; The order is not important.
20; CHECK: pxor
21; CHECK: movdqa
22
23; The instructions in the loop must all be integer domain as well.
24; CHECK: while.body
25; CHECK: pand
26; CHECK: movdqa
27; CHECK: movdqa
28; Finally, the controlling integer-only instruction.
29; CHECK: paddd
30while.body:
31  %p.addr.04 = phi <4 x i32>* [ %incdec.ptr, %while.body ], [ %p, %entry ]
32  %n.addr.03 = phi i32 [ %dec, %while.body ], [ %n, %entry ]
33  %x.02 = phi <4 x i32> [ %add, %while.body ], [ zeroinitializer, %entry ]
34  %dec = add nsw i32 %n.addr.03, -1
35  %and = and <4 x i32> %x.02, <i32 127, i32 127, i32 127, i32 127>
36  %incdec.ptr = getelementptr inbounds <4 x i32>* %p.addr.04, i64 1
37  store <4 x i32> %and, <4 x i32>* %p.addr.04, align 16
38  %0 = load <4 x i32>* %incdec.ptr, align 16
39  %add = shl <4 x i32> %0, <i32 1, i32 1, i32 1, i32 1>
40  %tobool = icmp eq i32 %dec, 0
41  br i1 %tobool, label %while.end, label %while.body
42
43while.end:
44  ret void
45}
46
47; CHECK: f2
48; CHECK: for.body
49;
50; This loop contains two cvtsi2ss instructions that update the same xmm
51; register.  Verify that the execution dependency fix pass breaks those
52; dependencies by inserting xorps instructions.
53;
54; If the register allocator chooses different registers for the two cvtsi2ss
55; instructions, they are still dependent on themselves.
56; CHECK: xorps [[XMM1:%xmm[0-9]+]]
57; CHECK: , [[XMM1]]
58; CHECK: cvtsi2ssl %{{.*}}, [[XMM1]]
59; CHECK: xorps [[XMM2:%xmm[0-9]+]]
60; CHECK: , [[XMM2]]
61; CHECK: cvtsi2ssl %{{.*}}, [[XMM2]]
62;
63define float @f2(i32 %m) nounwind uwtable readnone ssp {
64entry:
65  %tobool3 = icmp eq i32 %m, 0
66  br i1 %tobool3, label %for.end, label %for.body
67
68for.body:                                         ; preds = %entry, %for.body
69  %m.addr.07 = phi i32 [ %dec, %for.body ], [ %m, %entry ]
70  %s1.06 = phi float [ %add, %for.body ], [ 0.000000e+00, %entry ]
71  %s2.05 = phi float [ %add2, %for.body ], [ 0.000000e+00, %entry ]
72  %n.04 = phi i32 [ %inc, %for.body ], [ 1, %entry ]
73  %conv = sitofp i32 %n.04 to float
74  %add = fadd float %s1.06, %conv
75  %conv1 = sitofp i32 %m.addr.07 to float
76  %add2 = fadd float %s2.05, %conv1
77  %inc = add nsw i32 %n.04, 1
78  %dec = add nsw i32 %m.addr.07, -1
79  %tobool = icmp eq i32 %dec, 0
80  br i1 %tobool, label %for.end, label %for.body
81
82for.end:                                          ; preds = %for.body, %entry
83  %s1.0.lcssa = phi float [ 0.000000e+00, %entry ], [ %add, %for.body ]
84  %s2.0.lcssa = phi float [ 0.000000e+00, %entry ], [ %add2, %for.body ]
85  %sub = fsub float %s1.0.lcssa, %s2.0.lcssa
86  ret float %sub
87}
88