1; These are tests for SSE3 codegen. 2 3; RUN: llc < %s -march=x86-64 -mcpu=nocona -mtriple=i686-apple-darwin9 -O3 \ 4; RUN: | FileCheck %s --check-prefix=X64 5 6; Test for v8xi16 lowering where we extract the first element of the vector and 7; placed it in the second element of the result. 8 9define void @t0(<8 x i16>* %dest, <8 x i16>* %old) nounwind { 10entry: 11 %tmp3 = load <8 x i16>* %old 12 %tmp6 = shufflevector <8 x i16> %tmp3, 13 <8 x i16> < i16 0, i16 undef, i16 undef, i16 undef, i16 undef, i16 undef, i16 undef, i16 undef >, 14 <8 x i32> < i32 8, i32 0, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef > 15 store <8 x i16> %tmp6, <8 x i16>* %dest 16 ret void 17 18; X64-LABEL: t0: 19; X64: movdqa (%rsi), %xmm0 20; X64: pslldq $2, %xmm0 21; X64: movdqa %xmm0, (%rdi) 22; X64: ret 23} 24 25define <8 x i16> @t1(<8 x i16>* %A, <8 x i16>* %B) nounwind { 26 %tmp1 = load <8 x i16>* %A 27 %tmp2 = load <8 x i16>* %B 28 %tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> < i32 8, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7 > 29 ret <8 x i16> %tmp3 30 31; X64-LABEL: t1: 32; X64: movdqa (%rdi), %xmm0 33; X64: pinsrw $0, (%rsi), %xmm0 34; X64: ret 35} 36 37define <8 x i16> @t2(<8 x i16> %A, <8 x i16> %B) nounwind { 38 %tmp = shufflevector <8 x i16> %A, <8 x i16> %B, <8 x i32> < i32 9, i32 1, i32 2, i32 9, i32 4, i32 5, i32 6, i32 7 > 39 ret <8 x i16> %tmp 40; X64-LABEL: t2: 41; X64: pextrw $1, %xmm1, %eax 42; X64: pinsrw $0, %eax, %xmm0 43; X64: pinsrw $3, %eax, %xmm0 44; X64: ret 45} 46 47define <8 x i16> @t3(<8 x i16> %A, <8 x i16> %B) nounwind { 48 %tmp = shufflevector <8 x i16> %A, <8 x i16> %A, <8 x i32> < i32 8, i32 3, i32 2, i32 13, i32 7, i32 6, i32 5, i32 4 > 49 ret <8 x i16> %tmp 50; X64-LABEL: t3: 51; X64: pextrw $5, %xmm0, %eax 52; X64: pshuflw $44, %xmm0, %xmm0 53; X64: pshufhw $27, %xmm0, %xmm0 54; X64: pinsrw $3, %eax, %xmm0 55; X64: ret 56} 57 58define <8 x i16> @t4(<8 x i16> %A, <8 x i16> %B) nounwind { 59 %tmp = shufflevector <8 x i16> %A, <8 x i16> %B, <8 x i32> < i32 0, i32 7, i32 2, i32 3, i32 1, i32 5, i32 6, i32 5 > 60 ret <8 x i16> %tmp 61; X64-LABEL: t4: 62; X64: pextrw $7, [[XMM0:%xmm[0-9]+]], %eax 63; X64: pshufhw $100, [[XMM0]], [[XMM1:%xmm[0-9]+]] 64; X64: pinsrw $1, %eax, [[XMM1]] 65; X64: pextrw $1, [[XMM0]], %eax 66; X64: pinsrw $4, %eax, %xmm{{[0-9]}} 67; X64: ret 68} 69 70define <8 x i16> @t5(<8 x i16> %A, <8 x i16> %B) nounwind { 71 %tmp = shufflevector <8 x i16> %A, <8 x i16> %B, <8 x i32> < i32 8, i32 9, i32 0, i32 1, i32 10, i32 11, i32 2, i32 3 > 72 ret <8 x i16> %tmp 73; X64: t5: 74; X64: movlhps %xmm1, %xmm0 75; X64: pshufd $114, %xmm0, %xmm0 76; X64: ret 77} 78 79define <8 x i16> @t6(<8 x i16> %A, <8 x i16> %B) nounwind { 80 %tmp = shufflevector <8 x i16> %A, <8 x i16> %B, <8 x i32> < i32 8, i32 9, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7 > 81 ret <8 x i16> %tmp 82; X64: t6: 83; X64: movss %xmm1, %xmm0 84; X64: ret 85} 86 87define <8 x i16> @t7(<8 x i16> %A, <8 x i16> %B) nounwind { 88 %tmp = shufflevector <8 x i16> %A, <8 x i16> %B, <8 x i32> < i32 0, i32 0, i32 3, i32 2, i32 4, i32 6, i32 4, i32 7 > 89 ret <8 x i16> %tmp 90; X64: t7: 91; X64: pshuflw $-80, %xmm0, %xmm0 92; X64: pshufhw $-56, %xmm0, %xmm0 93; X64: ret 94} 95 96define void @t8(<2 x i64>* %res, <2 x i64>* %A) nounwind { 97 %tmp = load <2 x i64>* %A 98 %tmp.upgrd.1 = bitcast <2 x i64> %tmp to <8 x i16> 99 %tmp0 = extractelement <8 x i16> %tmp.upgrd.1, i32 0 100 %tmp1 = extractelement <8 x i16> %tmp.upgrd.1, i32 1 101 %tmp2 = extractelement <8 x i16> %tmp.upgrd.1, i32 2 102 %tmp3 = extractelement <8 x i16> %tmp.upgrd.1, i32 3 103 %tmp4 = extractelement <8 x i16> %tmp.upgrd.1, i32 4 104 %tmp5 = extractelement <8 x i16> %tmp.upgrd.1, i32 5 105 %tmp6 = extractelement <8 x i16> %tmp.upgrd.1, i32 6 106 %tmp7 = extractelement <8 x i16> %tmp.upgrd.1, i32 7 107 %tmp8 = insertelement <8 x i16> undef, i16 %tmp2, i32 0 108 %tmp9 = insertelement <8 x i16> %tmp8, i16 %tmp1, i32 1 109 %tmp10 = insertelement <8 x i16> %tmp9, i16 %tmp0, i32 2 110 %tmp11 = insertelement <8 x i16> %tmp10, i16 %tmp3, i32 3 111 %tmp12 = insertelement <8 x i16> %tmp11, i16 %tmp6, i32 4 112 %tmp13 = insertelement <8 x i16> %tmp12, i16 %tmp5, i32 5 113 %tmp14 = insertelement <8 x i16> %tmp13, i16 %tmp4, i32 6 114 %tmp15 = insertelement <8 x i16> %tmp14, i16 %tmp7, i32 7 115 %tmp15.upgrd.2 = bitcast <8 x i16> %tmp15 to <2 x i64> 116 store <2 x i64> %tmp15.upgrd.2, <2 x i64>* %res 117 ret void 118; X64: t8: 119; X64: pshuflw $-58, (%rsi), %xmm0 120; X64: pshufhw $-58, %xmm0, %xmm0 121; X64: movdqa %xmm0, (%rdi) 122; X64: ret 123} 124 125define void @t9(<4 x float>* %r, <2 x i32>* %A) nounwind { 126 %tmp = load <4 x float>* %r 127 %tmp.upgrd.3 = bitcast <2 x i32>* %A to double* 128 %tmp.upgrd.4 = load double* %tmp.upgrd.3 129 %tmp.upgrd.5 = insertelement <2 x double> undef, double %tmp.upgrd.4, i32 0 130 %tmp5 = insertelement <2 x double> %tmp.upgrd.5, double undef, i32 1 131 %tmp6 = bitcast <2 x double> %tmp5 to <4 x float> 132 %tmp.upgrd.6 = extractelement <4 x float> %tmp, i32 0 133 %tmp7 = extractelement <4 x float> %tmp, i32 1 134 %tmp8 = extractelement <4 x float> %tmp6, i32 0 135 %tmp9 = extractelement <4 x float> %tmp6, i32 1 136 %tmp10 = insertelement <4 x float> undef, float %tmp.upgrd.6, i32 0 137 %tmp11 = insertelement <4 x float> %tmp10, float %tmp7, i32 1 138 %tmp12 = insertelement <4 x float> %tmp11, float %tmp8, i32 2 139 %tmp13 = insertelement <4 x float> %tmp12, float %tmp9, i32 3 140 store <4 x float> %tmp13, <4 x float>* %r 141 ret void 142; X64: t9: 143; X64: movaps (%rdi), %xmm0 144; X64: movhps (%rsi), %xmm0 145; X64: movaps %xmm0, (%rdi) 146; X64: ret 147} 148 149 150 151; FIXME: This testcase produces icky code. It can be made much better! 152; PR2585 153 154@g1 = external constant <4 x i32> 155@g2 = external constant <4 x i16> 156 157define internal void @t10() nounwind { 158 load <4 x i32>* @g1, align 16 159 bitcast <4 x i32> %1 to <8 x i16> 160 shufflevector <8 x i16> %2, <8 x i16> undef, <8 x i32> < i32 0, i32 2, i32 4, i32 6, i32 undef, i32 undef, i32 undef, i32 undef > 161 bitcast <8 x i16> %3 to <2 x i64> 162 extractelement <2 x i64> %4, i32 0 163 bitcast i64 %5 to <4 x i16> 164 store <4 x i16> %6, <4 x i16>* @g2, align 8 165 ret void 166; X64: t10: 167; X64: pextrw $4, [[X0:%xmm[0-9]+]], %e{{..}} 168; X64: pextrw $6, [[X0]], %e{{..}} 169; X64: movlhps [[X0]], [[X0]] 170; X64: pshuflw $8, [[X0]], [[X0]] 171; X64: pinsrw $2, %e{{..}}, [[X0]] 172; X64: pinsrw $3, %e{{..}}, [[X0]] 173} 174 175 176; Pack various elements via shuffles. 177define <8 x i16> @t11(<8 x i16> %T0, <8 x i16> %T1) nounwind readnone { 178entry: 179 %tmp7 = shufflevector <8 x i16> %T0, <8 x i16> %T1, <8 x i32> < i32 1, i32 8, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef , i32 undef > 180 ret <8 x i16> %tmp7 181 182; X64-LABEL: t11: 183; X64: movd %xmm1, %eax 184; X64: movlhps %xmm0, %xmm0 185; X64: pshuflw $1, %xmm0, %xmm0 186; X64: pinsrw $1, %eax, %xmm0 187; X64: ret 188} 189 190 191define <8 x i16> @t12(<8 x i16> %T0, <8 x i16> %T1) nounwind readnone { 192entry: 193 %tmp9 = shufflevector <8 x i16> %T0, <8 x i16> %T1, <8 x i32> < i32 0, i32 1, i32 undef, i32 undef, i32 3, i32 11, i32 undef , i32 undef > 194 ret <8 x i16> %tmp9 195 196; X64-LABEL: t12: 197; X64: pextrw $3, %xmm1, %eax 198; X64: movlhps %xmm0, %xmm0 199; X64: pshufhw $3, %xmm0, %xmm0 200; X64: pinsrw $5, %eax, %xmm0 201; X64: ret 202} 203 204 205define <8 x i16> @t13(<8 x i16> %T0, <8 x i16> %T1) nounwind readnone { 206entry: 207 %tmp9 = shufflevector <8 x i16> %T0, <8 x i16> %T1, <8 x i32> < i32 8, i32 9, i32 undef, i32 undef, i32 11, i32 3, i32 undef , i32 undef > 208 ret <8 x i16> %tmp9 209; X64-LABEL: t13: 210; X64: punpcklqdq %xmm0, %xmm1 211; X64: pextrw $3, %xmm1, %eax 212; X64: pshufd $52, %xmm1, %xmm0 213; X64: pinsrw $4, %eax, %xmm0 214; X64: ret 215} 216 217 218define <8 x i16> @t14(<8 x i16> %T0, <8 x i16> %T1) nounwind readnone { 219entry: 220 %tmp9 = shufflevector <8 x i16> %T0, <8 x i16> %T1, <8 x i32> < i32 8, i32 9, i32 undef, i32 undef, i32 undef, i32 2, i32 undef , i32 undef > 221 ret <8 x i16> %tmp9 222; X64-LABEL: t14: 223; X64: punpcklqdq %xmm0, %xmm1 224; X64: pshufhw $8, %xmm1, %xmm0 225; X64: ret 226} 227 228 229; FIXME: t15 is worse off from disabling of scheduler 2-address hack. 230define <8 x i16> @t15(<8 x i16> %T0, <8 x i16> %T1) nounwind readnone { 231entry: 232 %tmp8 = shufflevector <8 x i16> %T0, <8 x i16> %T1, <8 x i32> < i32 undef, i32 undef, i32 7, i32 2, i32 8, i32 undef, i32 undef , i32 undef > 233 ret <8 x i16> %tmp8 234; X64: t15: 235; X64: pextrw $7, %xmm0, %eax 236; X64: punpcklqdq %xmm1, %xmm0 237; X64: pshuflw $-128, %xmm0, %xmm0 238; X64: pinsrw $2, %eax, %xmm0 239; X64: ret 240} 241 242 243; Test yonah where we convert a shuffle to pextrw and pinrsw 244define <16 x i8> @t16(<16 x i8> %T0) nounwind readnone { 245entry: 246 %tmp8 = shufflevector <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 1, i8 1, i8 1, i8 1, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, <16 x i8> %T0, <16 x i32> < i32 0, i32 1, i32 16, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef , i32 undef > 247 %tmp9 = shufflevector <16 x i8> %tmp8, <16 x i8> %T0, <16 x i32> < i32 0, i32 1, i32 2, i32 17, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef , i32 undef > 248 ret <16 x i8> %tmp9 249; X64: t16: 250; X64: pextrw $8, %xmm0, %eax 251; X64: pslldq $2, %xmm0 252; X64: pextrw $1, %xmm0, %ecx 253; X64: movzbl %cl, %ecx 254; X64: orl %eax, %ecx 255; X64: pinsrw $1, %ecx, %xmm0 256; X64: ret 257} 258 259; rdar://8520311 260define <4 x i32> @t17() nounwind { 261entry: 262; X64-LABEL: t17: 263; X64: movddup (%rax), %xmm0 264 %tmp1 = load <4 x float>* undef, align 16 265 %tmp2 = shufflevector <4 x float> %tmp1, <4 x float> undef, <4 x i32> <i32 4, i32 1, i32 2, i32 3> 266 %tmp3 = load <4 x float>* undef, align 16 267 %tmp4 = shufflevector <4 x float> %tmp2, <4 x float> undef, <4 x i32> <i32 undef, i32 undef, i32 0, i32 1> 268 %tmp5 = bitcast <4 x float> %tmp3 to <4 x i32> 269 %tmp6 = shufflevector <4 x i32> %tmp5, <4 x i32> undef, <4 x i32> <i32 undef, i32 undef, i32 0, i32 1> 270 %tmp7 = and <4 x i32> %tmp6, <i32 undef, i32 undef, i32 -1, i32 0> 271 ret <4 x i32> %tmp7 272} 273