1; RUN: llc < %s -mcpu=corei7 -march=x86 -mattr=+sse2  | FileCheck %s -check-prefix=X32
2; RUN: llc < %s -mcpu=corei7 -mtriple=x86_64-linux | FileCheck %s -check-prefix=X64
3; RUN: llc < %s -mcpu=corei7 -mtriple=x86_64-win32 | FileCheck %s -check-prefix=X64
4
5; Though it is undefined, we want xor undef,undef to produce zero.
6define <4 x i32> @test1() nounwind {
7	%tmp = xor <4 x i32> undef, undef
8	ret <4 x i32> %tmp
9
10; X32-LABEL: test1:
11; X32:	xorps	%xmm0, %xmm0
12; X32:	ret
13}
14
15; Though it is undefined, we want xor undef,undef to produce zero.
16define i32 @test2() nounwind{
17	%tmp = xor i32 undef, undef
18	ret i32 %tmp
19; X32-LABEL: test2:
20; X32:	xorl	%eax, %eax
21; X32:	ret
22}
23
24define i32 @test3(i32 %a, i32 %b) nounwind  {
25entry:
26        %tmp1not = xor i32 %b, -2
27	%tmp3 = and i32 %tmp1not, %a
28        %tmp4 = lshr i32 %tmp3, 1
29        ret i32 %tmp4
30
31; X64-LABEL: test3:
32; X64:	notl
33; X64:	andl
34; X64:	shrl
35; X64:	ret
36
37; X32-LABEL: test3:
38; X32: 	movl	8(%esp), %eax
39; X32: 	notl	%eax
40; X32: 	andl	4(%esp), %eax
41; X32: 	shrl	%eax
42; X32: 	ret
43}
44
45define i32 @test4(i32 %a, i32 %b) nounwind  {
46entry:
47        br label %bb
48bb:
49	%b_addr.0 = phi i32 [ %b, %entry ], [ %tmp8, %bb ]
50        %a_addr.0 = phi i32 [ %a, %entry ], [ %tmp3, %bb ]
51	%tmp3 = xor i32 %a_addr.0, %b_addr.0
52        %tmp4not = xor i32 %tmp3, 2147483647
53        %tmp6 = and i32 %tmp4not, %b_addr.0
54        %tmp8 = shl i32 %tmp6, 1
55        %tmp10 = icmp eq i32 %tmp8, 0
56	br i1 %tmp10, label %bb12, label %bb
57bb12:
58	ret i32 %tmp3
59
60; X64-LABEL: test4:
61; X64:    notl	[[REG:%[a-z]+]]
62; X64:    andl	{{.*}}[[REG]]
63; X32-LABEL: test4:
64; X32:    notl	[[REG:%[a-z]+]]
65; X32:    andl	{{.*}}[[REG]]
66}
67
68define i16 @test5(i16 %a, i16 %b) nounwind  {
69entry:
70        br label %bb
71bb:
72	%b_addr.0 = phi i16 [ %b, %entry ], [ %tmp8, %bb ]
73        %a_addr.0 = phi i16 [ %a, %entry ], [ %tmp3, %bb ]
74	%tmp3 = xor i16 %a_addr.0, %b_addr.0
75        %tmp4not = xor i16 %tmp3, 32767
76        %tmp6 = and i16 %tmp4not, %b_addr.0
77        %tmp8 = shl i16 %tmp6, 1
78        %tmp10 = icmp eq i16 %tmp8, 0
79	br i1 %tmp10, label %bb12, label %bb
80bb12:
81	ret i16 %tmp3
82; X64-LABEL: test5:
83; X64:    notl	[[REG:%[a-z]+]]
84; X64:    andl	{{.*}}[[REG]]
85; X32-LABEL: test5:
86; X32:    notl	[[REG:%[a-z]+]]
87; X32:    andl	{{.*}}[[REG]]
88}
89
90define i8 @test6(i8 %a, i8 %b) nounwind  {
91entry:
92        br label %bb
93bb:
94	%b_addr.0 = phi i8 [ %b, %entry ], [ %tmp8, %bb ]
95        %a_addr.0 = phi i8 [ %a, %entry ], [ %tmp3, %bb ]
96	%tmp3 = xor i8 %a_addr.0, %b_addr.0
97        %tmp4not = xor i8 %tmp3, 127
98        %tmp6 = and i8 %tmp4not, %b_addr.0
99        %tmp8 = shl i8 %tmp6, 1
100        %tmp10 = icmp eq i8 %tmp8, 0
101	br i1 %tmp10, label %bb12, label %bb
102bb12:
103	ret i8 %tmp3
104; X64-LABEL: test6:
105; X64:    notb	[[REG:%[a-z]+]]
106; X64:    andb	{{.*}}[[REG]]
107; X32-LABEL: test6:
108; X32:    notb	[[REG:%[a-z]+]]
109; X32:    andb	{{.*}}[[REG]]
110}
111
112define i32 @test7(i32 %a, i32 %b) nounwind  {
113entry:
114        br label %bb
115bb:
116	%b_addr.0 = phi i32 [ %b, %entry ], [ %tmp8, %bb ]
117        %a_addr.0 = phi i32 [ %a, %entry ], [ %tmp3, %bb ]
118	%tmp3 = xor i32 %a_addr.0, %b_addr.0
119        %tmp4not = xor i32 %tmp3, 2147483646
120        %tmp6 = and i32 %tmp4not, %b_addr.0
121        %tmp8 = shl i32 %tmp6, 1
122        %tmp10 = icmp eq i32 %tmp8, 0
123	br i1 %tmp10, label %bb12, label %bb
124bb12:
125	ret i32 %tmp3
126; X64-LABEL: test7:
127; X64:    xorl	$2147483646, [[REG:%[a-z]+]]
128; X64:    andl	{{.*}}[[REG]]
129; X32-LABEL: test7:
130; X32:    xorl	$2147483646, [[REG:%[a-z]+]]
131; X32:    andl	{{.*}}[[REG]]
132}
133
134define i32 @test8(i32 %a) nounwind {
135; rdar://7553032
136entry:
137  %t1 = sub i32 0, %a
138  %t2 = add i32 %t1, -1
139  ret i32 %t2
140; X64-LABEL: test8:
141; X64:   notl {{%eax|%edi|%ecx}}
142; X32-LABEL: test8:
143; X32:   notl %eax
144}
145
146define i32 @test9(i32 %a) nounwind {
147  %1 = and i32 %a, 4096
148  %2 = xor i32 %1, 4096
149  ret i32 %2
150; X64-LABEL: test9:
151; X64:    notl	[[REG:%[a-z]+]]
152; X64:    andl	{{.*}}[[REG:%[a-z]+]]
153; X32-LABEL: test9:
154; X32:    notl	[[REG:%[a-z]+]]
155; X32:    andl	{{.*}}[[REG:%[a-z]+]]
156}
157
158; PR15948
159define <4 x i32> @test10(<4 x i32> %a) nounwind {
160  %1 = and <4 x i32> %a, <i32 4096, i32 4096, i32 4096, i32 4096>
161  %2 = xor <4 x i32> %1, <i32 4096, i32 4096, i32 4096, i32 4096>
162  ret <4 x i32> %2
163; X64-LABEL: test10:
164; X64:    andnps
165; X32-LABEL: test10:
166; X32:    andnps
167}
168
169define i32 @PR17487(i1 %tobool) {
170  %tmp = insertelement <2 x i1> undef, i1 %tobool, i32 1
171  %tmp1 = zext <2 x i1> %tmp to <2 x i64>
172  %tmp2 = xor <2 x i64> %tmp1, <i64 1, i64 1>
173  %tmp3 = extractelement <2 x i64> %tmp2, i32 1
174  %add = add nsw i64 0, %tmp3
175  %cmp6 = icmp ne i64 %add, 1
176  %conv7 = zext i1 %cmp6 to i32
177  ret i32 %conv7
178
179; X64-LABEL: PR17487:
180; X64: andn
181; X32-LABEL: PR17487:
182; X32: andn
183}
184