1# RUN: not llvm-mc -disassemble %s -mcpu cortex-a8 -triple thumbv7 2>&1 | FileCheck %s 2 3# This file is checking Thumbv7 encodings which are globally invalid, usually due 4# to the constraints of the instructions not being met. For example invalid 5# combinations of registers. 6 7#------------------------------------------------------------------------------ 8# Undefined encoding for b.cc 9#------------------------------------------------------------------------------ 10 11# Opcode=1894 Name=t2Bcc Format=ARM_FORMAT_THUMBFRM(25) 12# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 13# ------------------------------------------------------------------------------------------------- 14# | 1: 1: 1: 1| 0: 1: 1: 1| 1: 0: 1: 0| 1: 1: 1: 1| 1: 0: 0: 0| 1: 0: 1: 1| 0: 1: 0: 0| 0: 1: 0: 0| 15# ------------------------------------------------------------------------------------------------- 16# 17# A8.6.16 B 18# if cond<3:1> == '111' then SEE "Related Encodings" 19 20[0xaf 0xf7 0x44 0x8b] 21# CHECK: warning: invalid instruction encoding 22# CHECK-NEXT: [0xaf 0xf7 0x44 0x8b] 23 24# Opcode=2249 Name=tBcc Format=ARM_FORMAT_THUMBFRM(25) 25# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 26# ------------------------------------------------------------------------------------------------- 27# | 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0| 1: 1: 0: 1| 1: 1: 1: 0| 0: 1: 1: 0| 1: 1: 1: 1| 28# ------------------------------------------------------------------------------------------------- 29# 30# if cond = '1110' then UNDEFINED 31[0x6f 0xde] 32# CHECK: invalid instruction encoding 33# CHECK-NEXT: [0x6f 0xde] 34 35#------------------------------------------------------------------------------ 36# Undefined encoding for it 37#------------------------------------------------------------------------------ 38 39[0xff 0xbf 0x6b 0x80 0x00 0x75] 40# CHECK: potentially undefined instruction encoding 41# CHECK-NEXT: [0xff 0xbf 0x6b 0x80 0x00 0x75] 42 43[0x50 0xbf] # hint #5; legal as the third instruction for the iteee above 44 45# Two warnings from this block since there are two instructions in there 46[0xdb 0xbf 0x42 0xbb] 47# CHECK: potentially undefined instruction encoding 48# CHECK-NEXT: [0xdb 0xbf 0x42 0xbb] 49# CHECK: potentially undefined instruction encoding 50# CHECK-NEXT: [0xdb 0xbf 0x42 0xbb] 51 52#------------------------------------------------------------------------------ 53# Undefined encoding for ldm 54#------------------------------------------------------------------------------ 55 56# Writeback is not allowed is Rn is in the target register list. 57[0xb4 0xe8 0x34 0x04] 58# CHECK: potentially undefined instruction encoding 59# CHECK-NEXT: [0xb4 0xe8 0x34 0x04] 60 61 62#------------------------------------------------------------------------------ 63# Undefined encoding for ldrd 64#------------------------------------------------------------------------------ 65 66# Opcode=1930 Name=t2LDRD_PRE Format=ARM_FORMAT_THUMBFRM(25) 67# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 68# ------------------------------------------------------------------------------------------------- 69# | 1: 1: 1: 0| 1: 0: 0: 1| 1: 1: 1: 1| 1: 1: 1: 1| 1: 1: 1: 0| 1: 0: 1: 1| 0: 0: 0: 0| 0: 0: 0: 0| 70# ------------------------------------------------------------------------------------------------- 71# 72# A8.6.66 LDRD (immediate) 73# if Rn = '1111' then SEE LDRD (literal) 74# A8.6.67 LDRD (literal) 75# Inst{21} = 0 76 77[0xff 0xe9 0x0 0xeb] 78# CHECK: potentially undefined 79# CHECK-NEXT: [0xff 0xe9 0x0 0xeb] 80 81 82#------------------------------------------------------------------------------ 83# Undefined encodings for ldrbt 84#------------------------------------------------------------------------------ 85 86# Opcode=1922 Name=t2LDRBT Format=ARM_FORMAT_THUMBFRM(25) 87# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 88# ------------------------------------------------------------------------------------------------- 89# | 1: 1: 1: 1| 1: 0: 0: 0| 0: 0: 0: 1| 0: 0: 0: 0| 1: 1: 1: 1| 1: 1: 1: 0| 0: 0: 0: 0| 0: 0: 1: 1| 90# ------------------------------------------------------------------------------------------------- 91# 92# The unpriviledged Load/Store cannot have SP or PC as Rt. 93[0x10 0xf8 0x3 0xfe] 94# CHECK: potentially undefined instruction encoding 95# CHECK-NEXT: [0x10 0xf8 0x3 0xfe] 96 97 98#------------------------------------------------------------------------------ 99# Undefined encodings for ldrsh 100#------------------------------------------------------------------------------ 101 102# invalid LDRSHs Rt=PC 103[0x30 0xf9 0x00 0xf0] 104# CHECK: invalid instruction encoding 105# CHECK-NEXT: [0x30 0xf9 0x00 0xf0] 106 107# invalid LDRSHi8 Rt=PC 108[0x30 0xf9 0x00 0xfc] 109# CHECK: invalid instruction encoding 110# CHECK-NEXT: [0x30 0xf9 0x00 0xfc] 111 112# invalid LDRSHi12 Rt=PC 113[0xb0 0xf9 0x00 0xf0] 114# CHECK: invalid instruction encoding 115# CHECK-NEXT: [0xb0 0xf9 0x00 0xf0] 116 117# Opcode=1954 Name=t2LDRSHi8 Format=ARM_FORMAT_THUMBFRM(25) 118# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 119# ------------------------------------------------------------------------------------------------- 120# | 1: 1: 1: 1| 1: 0: 0: 1| 0: 0: 1: 1| 0: 1: 0: 1| 1: 1: 1: 1| 1: 1: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0| 121# ------------------------------------------------------------------------------------------------- 122# 123# if Rt == '1111' and PUW == '100' then SEE "Unallocated memory hints" 124[0x35 0xf9 0x00 0xfc] 125# CHECK: invalid instruction encoding 126# CHECK-NEXT: [0x35 0xf9 0x00 0xfc] 127 128# Opcode=1953 Name=t2LDRSHi12 Format=ARM_FORMAT_THUMBFRM(25) 129# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 130# ------------------------------------------------------------------------------------------------- 131# | 1: 1: 1: 1| 1: 0: 0: 1| 1: 0: 1: 1| 0: 0: 1: 1| 1: 1: 1: 1| 1: 0: 0: 0| 1: 1: 0: 1| 1: 1: 1: 1| 132# ------------------------------------------------------------------------------------------------- 133# 134# if Rt = '1111' then SEE "Unallocated memory hints" 135[0xb3 0xf9 0xdf 0xf8] 136# CHECK: invalid instruction encoding 137# CHECK-NEXT: [0xb3 0xf9 0xdf 0xf8] 138 139 140#------------------------------------------------------------------------------ 141# Undefined encoding for push 142#------------------------------------------------------------------------------ 143 144# SP and PC are not allowed in the register list on STM instructions in Thumb2. 145[0x2d 0xe9 0xf7 0xb6] 146# CHECK: invalid instruction encoding 147# CHECK-NEXT: [0x2d 0xe9 0xf7 0xb6] 148 149 150#------------------------------------------------------------------------------ 151# Undefined encoding for stmia 152#------------------------------------------------------------------------------ 153 154# Opcode=2313 Name=tSTMIA_UPD Format=ARM_FORMAT_THUMBFRM(25) 155# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 156# ------------------------------------------------------------------------------------------------- 157# | 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0| 1: 1: 0: 0| 0: 1: 1: 1| 0: 0: 0: 0| 0: 0: 0: 0| 158# ------------------------------------------------------------------------------------------------- 159# 160# if BitCount(registers) < 1 then UNPREDICTABLE 161[0x00 0xc7] 162# CHECK: invalid instruction encoding 163# CHECK-NEXT: [0x00 0xc7] 164 165 166#------------------------------------------------------------------------------ 167# Undefined encodings for str 168#------------------------------------------------------------------------------ 169 170# invalid STRi12 Rn=PC 171[0xcf 0xf8 0x00 0x00] 172# CHECK: invalid instruction encoding 173# CHECK-NEXT: [0xcf 0xf8 0x00 0x00] 174 175# invalid STRi8 Rn=PC 176[0x4f 0xf8 0x00 0x0c] 177# CHECK: invalid instruction encoding 178# CHECK-NEXT: [0x4f 0xf8 0x00 0x0c] 179 180# invalid STRs Rn=PC 181[0x4f 0xf8 0x00 0x00] 182# CHECK: invalid instruction encoding 183# CHECK-NEXT: [0x4f 0xf8 0x00 0x00] 184 185# invalid STRBi12 Rn=PC 186[0x0f 0xf8 0x00 0x00] 187# CHECK: invalid instruction encoding 188# CHECK-NEXT: [0x0f 0xf8 0x00 0x00] 189 190# invalid STRBi8 Rn=PC 191[0x0f 0xf8 0x00 0x0c] 192# CHECK: invalid instruction encoding 193# CHECK-NEXT: [0x0f 0xf8 0x00 0x0c] 194 195# invalid STRBs Rn=PC 196[0x0f 0xf8 0x00 0x00] 197# CHECK: invalid instruction encoding 198# CHECK-NEXT: [0x0f 0xf8 0x00 0x00] 199 200# invalid STRHi12 Rn=PC 201[0xaf 0xf8 0x00 0x00] 202# CHECK: invalid instruction encoding 203# CHECK-NEXT: [0xaf 0xf8 0x00 0x00] 204 205# invalid STRHi8 Rn=PC 206[0x2f 0xf8 0x00 0x0c] 207# CHECK: invalid instruction encoding 208# CHECK-NEXT: [0x2f 0xf8 0x00 0x0c] 209 210# invalid STRHs Rn=PC 211[0x2f 0xf8 0x00 0x00] 212# CHECK: invalid instruction encoding 213# CHECK-NEXT: [0x2f 0xf8 0x00 0x00] 214 215# invalid STRBT Rn=PC 216[0x0f 0xf8 0x00 0x0e] 217# CHECK: invalid instruction encoding 218# CHECK-NEXT: [0x0f 0xf8 0x00 0x0e] 219 220# invalid STRHT Rn=PC 221[0x2f 0xf8 0x00 0x0e] 222# CHECK: invalid instruction encoding 223# CHECK-NEXT: [0x2f 0xf8 0x00 0x0e] 224 225# invalid STRT Rn=PC 226[0x4f 0xf8 0x00 0x0e] 227# CHECK: invalid instruction encoding 228# CHECK-NEXT: [0x4f 0xf8 0x00 0x0e] 229 230# Opcode=2137 Name=t2STR_POST Format=ARM_FORMAT_THUMBFRM(25) 231# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 232# ------------------------------------------------------------------------------------------------- 233# | 1: 1: 1: 1| 1: 0: 0: 0| 0: 1: 0: 0| 1: 1: 1: 1| 1: 1: 1: 0| 1: 0: 1: 1| 1: 1: 1: 1| 1: 1: 1: 1| 234# ------------------------------------------------------------------------------------------------- 235# 236# if Rn == '1111' then UNDEFINED 237 238[0x4f 0xf8 0xff 0xeb] 239# CHECK: invalid instruction encoding 240# CHECK-NEXT: [0x4f 0xf8 0xff 0xeb] 241 242#------------------------------------------------------------------------------ 243# Undefined encodings for strd 244#------------------------------------------------------------------------------ 245 246# Rt == Rn is UNPREDICTABLE 247[0xe4 0xe9 0x02 0x46] 248# CHECK: warning: potentially undefined instruction encoding 249# CHECK-NEXT: [0xe4 0xe9 0x02 0x46] 250 251#------------------------------------------------------------------------------ 252# Undefined encodings for NEON/VFP instructions with invalid predicate bits 253#------------------------------------------------------------------------------ 254 255# VABS 256[0x40 0xde 0x00 0x0a] 257# CHECK: invalid instruction encoding 258# CHECK-NEXT: [0x40 0xde 0x00 0x0a] 259 260 261# VMLA 262[0xf0 0xde 0xe0 0x0b] 263# CHECK: invalid instruction encoding 264# CHECK-NEXT: [0xf0 0xde 0xe0 0x0b] 265 266# VMOV/VDUP between scalar and core registers with invalid predicate bits (pred != 0b1110) 267 268# VMOV 269[0x00 0xde 0x10 0x0b] 270# CHECK: invalid instruction encoding 271# CHECK-NEXT: [0x00 0xde 0x10 0x0b] 272 273# VDUP 274[0xff 0xde 0xf0 0xfb] 275# CHECK: invalid instruction encoding 276# CHECK-NEXT: [0xff 0xde 0xf0 0xfb] 277 278 279#------------------------------------------------------------------------------ 280# Undefined encodings for NEON vld instructions 281#------------------------------------------------------------------------------ 282 283# size = '00' and index_align == '0001' so UNDEFINED 284[0xa0 0xf9 0x10 0x08] 285# CHECK: invalid instruction encoding 286# CHECK-NEXT: [0xa0 0xf9 0x10 0x08] 287 288 289# vld3 290 291# Opcode=871 Name=VLD3DUPd32_UPD Format=ARM_FORMAT_NLdSt(30) 292# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 293# ------------------------------------------------------------------------------------------------- 294# | 1: 1: 1: 1| 0: 1: 0: 0| 1: 0: 1: 0| 0: 0: 1: 0| 0: 0: 1: 0| 1: 1: 1: 0| 1: 0: 0: 1| 0: 0: 1: 0| 295# ------------------------------------------------------------------------------------------------- 296# 297# A8.6.315 VLD3 (single 3-element structure to all lanes) 298# The a bit must be encoded as 0. 299 300[0xa2 0xf9 0x92 0x2e] 301# CHECK: invalid instruction encoding 302# CHECK-NEXT: [0xa2 0xf9 0x92 0x2e] 303 304 305# Some vld4 ones 306# size == '11' and a == '0' so UNDEFINED 307[0xa0 0xf9 0xc0 0x0f] 308# CHECK: invalid instruction encoding 309# CHECK-NEXT: [0xa0 0xf9 0xc0 0x0f] 310 311[0xa0 0xf9 0x30 0x0b] 312# CHECK: invalid instruction encoding 313# CHECK-NEXT: [0xa0 0xf9 0x30 0x0b] 314 315 316# VLD1 multi-element, type=0b1010 align=0b11 317[0x24 0xf9 0xbf 0x8a] 318# CHECK: invalid instruction encoding 319# CHECK-NEXT: [0x24 0xf9 0xbf 0x8a] 320 321# VLD1 multi-element type=0b0111 align=0b1x 322[0x24 0xf9 0xbf 0x87] 323# CHECK: invalid instruction encoding 324# CHECK-NEXT: [0x24 0xf9 0xbf 0x87] 325 326# VLD1 multi-element type=0b0010 align=0b1x 327[0x24 0xf9 0xbf 0x86] 328# CHECK: invalid instruction encoding 329# CHECK-NEXT: [0x24 0xf9 0xbf 0x86] 330 331# VLD2 multi-element size=0b11 332[0x60 0xf9 0xcf 0x08] 333# CHECK: invalid instruction encoding 334# CHECK-NEXT: [0x60 0xf9 0xcf 0x08] 335 336# VLD2 multi-element type=0b1111 align=0b11 337[0x60 0xf9 0xbf 0x08] 338# CHECK: invalid instruction encoding 339# CHECK-NEXT: [0x60 0xf9 0xbf 0x08] 340 341# VLD2 multi-element type=0b1001 align=0b11 342[0x60 0xf9 0xbf 0x09] 343# CHECK: invalid instruction encoding 344# CHECK-NEXT: [0x60 0xf9 0xbf 0x09] 345 346# VLD3 multi-element size=0b11 347[0x60 0xf9 0x7f 0x04] 348# CHECK: invalid instruction encoding 349# CHECK-NEXT: [0x60 0xf9 0x7f 0x04] 350 351# VLD3 multi-element align=0b1x 352[0x60 0xf9 0xcf 0x04] 353# CHECK: invalid instruction encoding 354# CHECK-NEXT: [0x60 0xf9 0xcf 0x04] 355 356# VLD4 multi-element size=0b11 357[0x60 0xf9 0xcd 0x11] 358# CHECK: invalid instruction encoding 359# CHECK-NEXT: [0x60 0xf9 0xcd 0x11] 360 361 362#------------------------------------------------------------------------------ 363# Undefined encodings for NEON vst1 364#------------------------------------------------------------------------------ 365 366# size == '10' and index_align == '0001' so UNDEFINED 367[0x80 0xf9 0x10 0x08] 368# CHECK: invalid instruction encoding 369# CHECK-NEXT: [0x80 0xf9 0x10 0x08] 370 371# Opcode=1839 Name=VST1d8Twb_register Format=ARM_FORMAT_NLdSt(30) 372# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 373# ------------------------------------------------------------------------------------------------- 374# | 1: 1: 1: 1| 1: 0: 0: 1| 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0| 0: 1: 1: 0| 0: 0: 1: 0| 1: 1: 1: 1| 375# ------------------------------------------------------------------------------------------------- 376# 377# A8.6.391 VST1 (multiple single elements) 378# This encoding looks like: vst1.8 {d0,d1,d2}, [r0:128] 379# But bits 5-4 for the alignment of 128 encoded as align = 0b10, is available only if <list> 380# contains two or four registers. rdar://11220250 381[0x00 0xf9 0x2f 0x06] 382# CHECK: invalid instruction encoding 383# CHECK-NEXT: [0x00 0xf9 0x2f 0x06] 384 385#------------------------------------------------------------------------------ 386# Undefined encodings for NEON vst4 387#------------------------------------------------------------------------------ 388 389[0x80 0xf9 0x30 0x0b] 390# CHECK: invalid instruction encoding 391# CHECK-NEXT: [0x80 0xf9 0x30 0x0b] 392 393 394#------------------------------------------------------------------------------ 395# Unpredictable STMs 396#------------------------------------------------------------------------------ 397 398# 32-bit Thumb STM instructions cannot have a writeback register which appears 399# in the list. 400 401[0xa1,0xe8,0x07,0x04] 402# CHECK: warning: potentially undefined instruction encoding 403# CHECK-NEXT: [0xa1,0xe8,0x07,0x04] 404 405[0x21,0xe9,0x07,0x04] 406# CHECK: warning: potentially undefined instruction encoding 407# CHECK-NEXT: [0x21,0xe9,0x07,0x04] 408